用小脚丫STEP FPGA开发板的数码管、三色灯、sw实现：1.Sw4来控制启停，当Sw4往下拨开始计数；2.从0开始用两个数码管计数，每隔3s加一个数；3.加到15后，三色灯循环闪烁，按照红色1秒，蓝色1秒，黄色1s这个循环闪烁持续10s；4.重复步骤2和3，直到Sw4往上拨的时候停止的Quarter代码和FPGA管脚设置

这里给出了基于Verilog的Quarter代码和基于小脚丫STEP FPGA开发板的管脚设置。请注意，由于每个开发板的管脚分配可能不同，您需要根据您的开发板手册进行适当的调整。

// Quarter代码
module counter(
    input clk,
    input reset,
    input sw4,
    output reg [7:0] digit1,
    output reg [7:0] digit2,
    output reg [2:0] led
    );

    reg [3:0] count;
    reg [19:0] timer;
    reg start;

    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
            timer <= 0;
            start <= 0;
            digit1 <= 8'b00000000;
            digit2 <= 8'b00000000;
            led <= 3'b000;
        end else begin
            if (sw4 && !start) begin
                start <= 1;
                timer <= 0;
                count <= 0;
                digit1 <= 8'b00000000;
                digit2 <= 8'b00000000;
                led <= 3'b000;
            end else if (start) begin
                timer <= timer + 1;
                if (timer == 20000000) begin
                    timer <= 0;
                    count <= count + 1;
                    if (count == 16) begin
                        count <= 0;
                        led <= 3'b001;
                        timer <= 0;
                        for (int i = 0; i < 10; i = i + 1) begin
                            #20000000 led <= 3'b100;
                            #20000000 led <= 3'b010;
                            #20000000 led <= 3'b001;
                        end
                    end else begin
                        if (count % 2 == 0) begin
                            digit1 <= 8'b01111110;
                        end else begin
                            digit1 <= 8'b00000110;
                        end
                        digit2 <= {4'b0000, count};
                    end
                end
            end else begin
                digit1 <= 8'b00000000;
                digit2 <= 8'b00000000;
                led <= 3'b000;
            end
        end
    end

endmodule

接下来是FPGA管脚的设置：

// FPGA管脚设置
NET "digit1<0>" LOC = "P85" | IOSTANDARD = "LVCMOS33"; // 数码管1 a
NET "digit1<1>" LOC = "P86" | IOSTANDARD = "LVCMOS33"; // 数码管1 b
NET "digit1<2>" LOC = "P87" | IOSTANDARD = "LVCMOS33"; // 数码管1 c
NET "digit1<3>" LOC = "P88" | IOSTANDARD = "LVCMOS33"; // 数码管1 d
NET "digit1<4>" LOC = "P89" | IOSTANDARD = "LVCMOS33"; // 数码管1 e
NET "digit1<5>" LOC = "P90" | IOSTANDARD = "LVCMOS33"; // 数码管1 f
NET "digit1<6>" LOC = "P91" | IOSTANDARD = "LVCMOS33"; // 数码管1 g
NET "digit1<7>" LOC = "P92" | IOSTANDARD = "LVCMOS33"; // 数码管1 dp

NET "digit2<0>" LOC = "P93" | IOSTANDARD = "LVCMOS33"; // 数码管2 a
NET "digit2<1>" LOC = "P94" | IOSTANDARD = "LVCMOS33"; // 数码管2 b
NET "digit2<2>" LOC = "P97" | IOSTANDARD = "LVCMOS33"; // 数码管2 c
NET "digit2<3>" LOC = "P98" | IOSTANDARD = "LVCMOS33"; // 数码管2 d
NET "digit2<4>" LOC = "P99" | IOSTANDARD = "LVCMOS33"; // 数码管2 e
NET "digit2<5>" LOC = "P100" | IOSTANDARD = "LVCMOS33"; // 数码管2 f
NET "digit2<6>" LOC = "P101" | IOSTANDARD = "LVCMOS33"; // 数码管2 g
NET "digit2<7>" LOC = "P102" | IOSTANDARD = "LVCMOS33"; // 数码管2 dp

NET "led<0>" LOC = "P104" | IOSTANDARD = "LVCMOS33"; // 三色灯红
NET "led<1>" LOC = "P105" | IOSTANDARD = "LVCMOS33"; // 三色灯蓝
NET "led<2>" LOC = "P106" | IOSTANDARD = "LVCMOS33"; // 三色灯黄

NET "sw4" LOC = "P109" | IOSTANDARD = "LVCMOS33"; // 按钮
NET "clk" LOC = "P89" | IOSTANDARD = "LVCMOS33"; // 时钟
NET "reset" LOC = "P109" | IOSTANDARD = "LVCMOS33"; // 复位