Vivado实现图像去噪芯片设计代码和激励信号代码

实现图像去噪的芯片设计通常需要使用FPGA进行实现，而Vivado是一款常用的FPGA设计工具，以下是一个简单的图像去噪设计的代码示例和激励信号代码示例。

图像去噪芯片设计代码示例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity denoiser is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           input_valid : in STD_LOGIC;
           input_pixel : in STD_LOGIC_VECTOR (7 downto 0);
           output_valid : out STD_LOGIC;
           output_pixel : out STD_LOGIC_VECTOR (7 downto 0));
end denoiser;

architecture Behavioral of denoiser is

    -- 缓存区大小
    constant BUFFER_SIZE : integer := 9;
    
    -- 图像像素类型
    type pixel_type is array (0 to BUFFER_SIZE-1) of STD_LOGIC_VECTOR(7 downto 0); 

    -- 像素缓存区
    signal pixel_buffer : pixel_type := (others => (others => '0'));

    -- 输出像素
    signal output_pixel_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    
    -- 内部时钟计数器
    signal clock_counter : integer range 0 to BUFFER_SIZE-1 := 0;

    -- 内部行计数器
    signal row_counter : integer range 0 to 479 := 0;

    -- 内部列计数器
    signal col_counter : integer range 0 to 639 := 0;

    -- 图像像素总数
    constant PIXEL_COUNT : integer := 480 * 640;
    
    -- 当前像素是否为边缘像素
    function is_edge_pixel(row : integer; col : integer) return boolean is
    begin
        if (row = 0 or row = 479 or col = 0 or col = 639) then
            return true;
        else
            return false;
        end if;
    end function;
    
    -- 将像素插入缓存区
    procedure insert_pixel(pixel : STD_LOGIC_VECTOR(7 downto 0)) is
    begin
        pixel_buffer(clock_counter) <= pixel;
        clock_counter <= clock_counter + 1;
        if (clock_counter = BUFFER_SIZE) then
            clock_counter <= 0;
        end if;
    end procedure;

    -- 获取缓存区像素
    function get_pixel(row : integer; col : integer) return pixel_type is
        variable pixels : pixel_type;
    begin
        if (is_edge_pixel(row, col)) then
            pixels := (others => (others => '0'));
        else
            pixels(0) := pixel_buffer(0);
            pixels(1) := pixel_buffer(1);
            pixels(2) := pixel_buffer(2);
            pixels(3) := pixel_buffer(3);
            pixels(4) := pixel_buffer(4);
            pixels(5) := pixel_buffer(5);
            pixels(6) := pixel_buffer(6);
            pixels(7) := pixel_buffer(7);
            pixels(8) := pixel_buffer(8);
        end if;
        return pixels;
    end function;

begin

    process(clk)
        variable sum : integer range 0 to 255 := 0;
        variable count : integer range 0 to 8 := 0;
    begin
        if (rising_edge(clk)) then
            if (rst = '1') then
                pixel_buffer <= (others => (others => '0'));
                output_pixel_reg <= (others => '0');
                clock_counter <= 0;
                row_counter <= 0;
                col_counter <= 0;
                output_valid <= '0';
            else
                if (input_valid = '1') then
                    insert_pixel(input_pixel);
                    if (col_counter = 639) then
                        row_counter <= row_counter + 1;
                        col_counter <= 0;
                    else
                        col_counter <= col_counter + 1;
                    end if;
                end if;
                if (clock_counter = 0 and row_counter >= 1 and row_counter <= 478 and col_counter >= 1 and col_counter <= 638) then
                    for i in 0 to BUFFER_SIZE-1 loop
                        sum := sum + to_integer(unsigned(pixel_buffer(i)));
                        count := count + 1;
                    end loop;
                    output_pixel_reg <= std_logic_vector(to_unsigned(sum/count, 8));
                    output_valid <= '1';
                else
                    output_valid <= '0';
                end if;
            end if;
        end if;
    end process;

    output_pixel <= output_pixel_reg;

end Behavioral;

激励信号代码示例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity denoiser_tb is
end denoiser_tb;

architecture Behavioral of denoiser_tb is

    -- 时钟信号
    signal clk : STD_LOGIC := '0';
    
    -- 复位信号
    signal rst : STD_LOGIC := '1';
    
    -- 输入像素有效信号
    signal input_valid : STD_LOGIC := '0';
    
    -- 输入像素
    signal input_pixel : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    
    -- 输出像素有效信号
    signal output_valid : STD_LOGIC;
    
    -- 输出像素
    signal output_pixel : STD_LOGIC_VECTOR(7 downto 0);
    
begin

    -- 实例化待测设计
    uut : entity work.denoiser
        Port map (clk => clk,
                  rst => rst,
                  input_valid => input_valid,
                  input_pixel => input_pixel,
                  output_valid => output_valid,
                  output_pixel => output_pixel);

    -- 时钟信号生成
    clk_process : process
    begin
        while true loop
            clk <= not clk;
            wait for 10 ns;
        end loop;
    end process;

    -- 复位信号生成
    rst_process : process
    begin
        rst <= '1';
        wait for 100 ns;
        rst <= '0';
        wait;
    end process;
    
    -- 输入像素生成
    input_process : process
    begin
        input_valid <= '0';
        wait for 200 ns;
        for i in 0 to 479 loop
            for j in 0 to 639 loop
                input_valid <= '1';
                input_pixel <= std_logic_vector(to_unsigned(integer(random(255)), 8));
                wait for 10 ns;
                input_valid <= '0';
                wait for 10 ns;
            end loop;
        end loop;
        wait;
    end process;
    
    -- 输出像素检查
    output_process : process
    begin
        wait for 1000 ns;
        for i in 0 to 479 loop
            for j in 0 to 639 loop
                wait until output_valid = '1';
                assert output_pixel = input_pixel
                    report "Output pixel does not match input pixel" severity error;
                wait for 10 ns;
            end loop;
        end loop;
        wait;
    end process;

end Behavioral;