写一个systemverilog，实现有符号数转为无符号数补码

module signed_to_unsigned (input signed [31:0] signed_num,
output logic [31:0] unsigned_num);

always_comb begin
if (signed_num < 0) begin
unsigned_num = ~(-signed_num) + 1;
end else begin
unsigned_num = signed_num;
end
end

endmodule