利用verilog 设计8位加法器。（层次化设计方法。最低层为半加器：h_adder；然后是1位全加器f_adder；顶层为8位全加器f_adder_8）

以下是Verilog代码：

module h_adder(a, b, sum, carry);
  input a, b;
  output sum, carry;
  
  assign sum = a ^ b;
  assign carry = a & b;
endmodule

module f_adder(a, b, cin, sum, cout);
  input a, b, cin;
  output sum, cout;
  
  h_adder ha1(.a(a), .b(b), .sum(s1), .carry(c1));
  h_adder ha2(.a(s1), .b(cin), .sum(sum), .carry(c2));
  assign cout = c1 | c2;
endmodule

module f_adder_8(a, b, sum);
  input [7:0] a, b;
  output [7:0] sum;
  
  wire c0, c1, c2, c3, c4, c5, c6, c7;
  
  f_adder fa1(.a(a[0]), .b(b[0]), .cin(0), .sum(sum[0]), .cout(c0));
  f_adder fa2(.a(a[1]), .b(b[1]), .cin(c0), .sum(sum[1]), .cout(c1));
  f_adder fa3(.a(a[2]), .b(b[2]), .cin(c1), .sum(sum[2]), .cout(c2));
  f_adder fa4(.a(a[3]), .b(b[3]), .cin(c2), .sum(sum[3]), .cout(c3));
  f_adder fa5(.a(a[4]), .b(b[4]), .cin(c3), .sum(sum[4]), .cout(c4));
  f_adder fa6(.a(a[5]), .b(b[5]), .cin(c4), .sum(sum[5]), .cout(c5));
  f_adder fa7(.a(a[6]), .b(b[6]), .cin(c5), .sum(sum[6]), .cout(c6));
  f_adder fa8(.a(a[7]), .b(b[7]), .cin(c6), .sum(sum[7]), .cout(c7));
endmodule

上述代码中，`h_adder`模块实现了半加器，`f_adder`模块实现了1位全加器，`f_adder_8`模块实现了8位全加器。在8位全加器中，使用了8个1位全加器，以实现8位的加法运算。