0、1、8、16、9、2、3、10、17、24、32、25、18、11、4、5、12、19、26 二进制转换规律
时间: 2023-10-04 19:12:59 浏览: 29
这个序列是以十进制数递增1的顺序排列的,但是它们的二进制形式却有规律。将它们的十进制数转换成二进制数,可以发现:
0:0000
1:0001
8:1000
16:10000
9:1001
2:0010
3:0011
10:1010
17:10001
24:11000
32:100000
25:11001
18:10010
11:1011
4:0100
5:0101
12:1100
19:10011
26:11010
可以发现,这些二进制数的最高位都是1或0,而且最高位为1的数的个数逐渐递增。每个最高位为1的数之后,都是在最高位为0的数中,按照二进制数的逆序排列的。例如,最高位为1的数是1000,之后是1001,1010,1011,然后是最高位为0的数中,逆序排列的0010,0011,0100,0101,0110,0111,然后是1100,1101,1110,1111。这个规律是因为,二进制数的最高位决定了它的大小,而最高位相同的数,其次高位越大,数值也就越大。因此,最高位为1的数会先排列,然后是最高位为0的数,按照逆序排列,这样可以保证按照大小递增的顺序排列。
相关问题
用Verilog实现 0、1、8、16、9、2、3、10、17、24、32、25、18、11、4、5、12、19、26
以下是一种实现方法:
```verilog
module sequence(
input clk,
output reg [5:0] output_number
);
reg [4:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
case(counter)
0: output_number <= 6'd0;
1: output_number <= 6'd1;
2: output_number <= 6'd8;
3: output_number <= 6'd16;
4: output_number <= 6'd9;
5: output_number <= 6'd2;
6: output_number <= 6'd3;
7: output_number <= 6'd10;
8: output_number <= 6'd17;
9: output_number <= 6'd24;
10: output_number <= 6'd32;
11: output_number <= 6'd25;
12: output_number <= 6'd18;
13: output_number <= 6'd11;
14: output_number <= 6'd4;
15: output_number <= 6'd5;
16: output_number <= 6'd12;
17: output_number <= 6'd19;
18: output_number <= 6'd26;
default: output_number <= 6'd0;
endcase
end
endmodule
```
该模块使用一个计数器来遍历给定的序列,并在每个时钟上升沿时输出序列中的下一个数字。计数器为 5 位,因为序列中的最大数字是 32(二进制为 100000)。计数器超出范围时,输出重置为 0。请注意,代码中的数字表示为 6 位二进制,因为我们需要 0。
用Verilog实现 0、1、8、16、9、2、3、10、17、24、32、25、18、11、4、5、12、19、26 禁止使用遍历
以下是使用状态机实现的Verilog代码:
```verilog
module forbidden_sequence_detector(
input clk,
input reset,
input data,
output reg detect
);
enum {START, S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18} state;
initial
begin
state = START;
detect = 0;
end
always @(posedge clk)
begin
if (reset)
begin
state = START;
detect = 0;
end
else
begin
case(state)
START:
begin
if (data == 0)
state = S0;
else if (data == 1)
state = S1;
else if (data == 2)
state = S2;
else if (data == 3)
state = S3;
else if (data == 4)
state = S4;
else if (data == 5)
state = S5;
else if (data == 8)
state = S6;
else
state = START;
end
S0:
begin
if (data == 1)
state = S1;
else
state = START;
end
S1:
begin
if (data == 8)
state = S6;
else if (data == 2)
state = S2;
else
state = START;
end
S2:
begin
if (data == 3)
state = S3;
else
state = START;
end
S3:
begin
if (data == 10)
state = S7;
else if (data == 4)
state = S4;
else
state = START;
end
S4:
begin
if (data == 5)
state = S5;
else
state = START;
end
S5:
begin
if (data == 12)
state = S8;
else if (data == 19)
state = S15;
else
state = START;
end
S6:
begin
if (data == 16)
state = S11;
else
state = START;
end
S7:
begin
if (data == 17)
state = S12;
else
state = START;
end
S8:
begin
if (data == 18)
state = S13;
else
state = START;
end
S11:
begin
if (data == 9)
state = S9;
else
state = START;
end
S9:
begin
if (data == 2)
state = S2;
else
state = START;
end
S12:
begin
if (data == 24)
state = S16;
else
state = START;
end
S13:
begin
if (data == 11)
state = S10;
else
state = START;
end
S10:
begin
if (data == 4)
state = S4;
else
state = START;
end
S15:
begin
if (data == 26)
state = S18;
else
state = START;
end
S16:
begin
if (data == 32)
state = S17;
else
state = START;
end
S17:
begin
if (data == 25)
state = S14;
else
state = START;
end
S18:
begin
detect = 1;
state = START;
end
default:
begin
state = START;
end
endcase
end
end
endmodule
```
该代码使用状态机实现,对于每个输入数据,根据当前状态进行状态转移。如果检测到数字序列,输出信号detect会被置为1。
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