library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity top_design is port( clk,rst,en : in std_logic; com: out std_logic_vector(3 downto 0); seg: out std_logic_vector(7 downto 0) ); end top_design; architecture Behavioral of top_design is component counter is port( bclk,rst,en : in std_logic; dcnt: out std_logic_vector(3 downto 0); add:out std_logic ); end component; component decoder is port( A : in std_logic_vector(2 downto 0); din:in std_logic_vector(15 downto 0); com:out std_logic_vector(3 downto 0); seg : out std_logic_vector(7 downto 0) ); end component; component gen_div is port ( clk:in std_logic;--输入时钟 bclk:out std_logic;--分频输出 rst:in std_logic--复位信号 ); end component; component A is Port ( bclk: in std_logic; A:out std_logic_vector(2 downto 0) ); end component; signal n1,n2,n3,n4: std_logic; signal bclk_signal:std_logic; signal x:std_logic_vector(2 downto 0):="000"; signal dout:std_logic_vector(15 downto 0):="0000000000000000"; begin u0 : counter port map(bclk_signal,rst,en,dout(3 downto 0),n1); u1 : counter port map(n1,rst,en,dout(7 downto 4),n2); u2 : counter port map(n2,rst,en,dout(11 downto 8),n3); u3 : counter port map(n3,rst,en,dout(15 downto 12),n4); u4 : decoder port map(x,dout,com,seg); u5 : gen_div port map( clk => clk, bclk => bclk_signal, rst => rst ); u6 :A port map(bclk_signal,x(2 downto 0)); end Behavioral;给这个文件写一个测试代码

以下是一个简单的测试代码，可以测试你的设计是否按照预期工作：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity top_design_tb is
end top_design_tb;

architecture Behavioral of top_design_tb is
component top_design is
port(
clk,rst,en : in std_logic;
com: out std_logic_vector(3 downto 0);
seg: out std_logic_vector(7 downto 0)
);
end component;

signal clk, rst, en : std_logic := '0';
signal com : std_logic_vector(3 downto 0);
signal seg : std_logic_vector(7 downto 0);

begin
uut: top_design port map (
clk => clk,
rst => rst,
en => en,
com => com,
seg => seg
);

clk_process: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

reset_process: process
begin
rst <= '1';
wait for 10 ns;
rst <= '0';
wait for 100 ns;
end process;

enable_process: process
begin
en <= '1';
wait for 100 ns;
en <= '0';
wait for 50 ns;
en <= '1';
wait for 100 ns;
en <= '0';
wait for 50 ns;
en <= '1';
wait for 100 ns;
en <= '0';
wait;
end process;

end Behavioral;