将下面的verilog文件改成VHDL文件“ module Time_sample( input i_clk , input i_rst , input i_ADC_clk , input [9:0] i_ADC , output o_ADC_valid , output[9:0] o_ADC ); parameter SAMPLE_TIME = 2000000000 ; parameter CLK_TIME = 20 ; parameter SIMPLE_CNT_NUM = SAMPLE_TIME/CLK_TIME ; wire [9:0] w_sync_ADC_data; wire w_empty ; sync_fifo sync_fifo_inst ( .wr_clk( i_ADC_clk ), .wr_rst( i_rst ), .rd_clk( i_clk ), .rd_rst( i_rst ), .din ( i_ADC ), .wr_en ( 1'b1 ), .rd_en ( 1'b1 ), .dout ( w_sync_ADC_data ), .full ( ), .empty ( w_empty ) ); reg [31:0] r_simple_cnt = 32'd0; always @(posedge i_clk)begin if(i_rst == 1'b1) r_simple_cnt <= 32'd0; else if(r_simple_cnt >= SIMPLE_CNT_NUM - 1'b1) r_simple_cnt <= 32'd0; else r_simple_cnt <= r_simple_cnt + 1'b1; end wire w_sample_en = (r_simple_cnt == SIMPLE_CNT_NUM - 1'b1); reg [7:0] r_ADC_data = 8'd0; reg r_ADC_valid = 1'd0 ; always @(posedge i_clk)begin if(i_rst == 1'b1)begin r_ADC_data <= 8'd0; r_ADC_valid <= 1'd0 ; end else if(w_sample_en)begin r_ADC_data <= w_sync_ADC_data; r_ADC_valid <= 1'b1; end else r_ADC_valid <= 1'b0; end assign o_ADC_valid = r_ADC_valid ; assign o_ADC = r_ADC_data ; endmodule ”

下面是将verilog文件改成VHDL文件后的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Time_sample is
  port (
    i_clk       : in  std_logic;
    i_rst       : in  std_logic;
    i_ADC_clk   : in  std_logic;
    i_ADC       : in  std_logic_vector(9 downto 0);
    o_ADC_valid : out std_logic;
    o_ADC       : out std_logic_vector(9 downto 0)
  );
end entity;

architecture rtl of Time_sample is
  constant SAMPLE_TIME    : integer := 2000000000;
  constant CLK_TIME       : integer := 20;
  constant SIMPLE_CNT_NUM : integer := SAMPLE_TIME/CLK_TIME;
  
  signal w_sync_ADC_data : std_logic_vector(9 downto 0);
  signal w_empty        : std_logic;
  
  component sync_fifo is
    port (
      wr_clk  : in  std_logic;
      wr_rst  : in  std_logic;
      rd_clk  : in  std_logic;
      rd_rst  : in  std_logic;
      din     : in  std_logic_vector(9 downto 0);
      wr_en   : in  std_logic;
      rd_en   : in  std_logic;
      dout    : out std_logic_vector(9 downto 0);
      full    : out std_logic;
      empty   : out std_logic
    );
  end component;
  
  signal r_simple_cnt : unsigned(31 downto 0) := (others => '0');
  signal r_ADC_data   : std_logic_vector(7 downto 0) := (others => '0');
  signal r_ADC_valid  : std_logic := '0';
  
begin
  sync_fifo_inst : sync_fifo
    port map (
      wr_clk => i_ADC_clk,
      wr_rst => i_rst,
      rd_clk => i_clk,
      rd_rst => i_rst,
      din    => i_ADC,
      wr_en  => '1',
      rd_en  => '1',
      dout   => w_sync_ADC_data,
      full   => open,
      empty  => w_empty
    );
  
  process (i_clk)
  begin
    if rising_edge(i_clk) then
      if i_rst = '1' then
        r_simple_cnt <= (others => '0');
      elsif r_simple_cnt >= SIMPLE_CNT_NUM - 1 then
        r_simple_cnt <= (others => '0');
      else
        r_simple_cnt <= r_simple_cnt + 1;
      end if;
    end if;
  end process;
  
  process (i_clk)
  begin
    if rising_edge(i_clk) then
      if i_rst = '1' then
        r_ADC_data  <= (others => '0');
        r_ADC_valid <= '0';
      elsif r_simple_cnt = SIMPLE_CNT_NUM - 1 then
        r_ADC_data  <= w_sync_ADC_data(7 downto 0);
        r_ADC_valid <= '1';
      else
        r_ADC_valid <= '0';
      end if;
    end if;
  end process;
  
  o_ADC_valid <= r_ADC_valid;
  o_ADC       <= r_ADC_data & w_sync_ADC_data(8 downto 0);
  
end architecture;

在VHDL中，需要使用`library`和`use`语句来导入需要使用的库和包。此外，VHDL中没有`wire`类型，需要使用`signal`来声明信号。VHDL中的`if`语句和Verilog中的`if`语句语法有所不同，需要使用`process`语句来实现。VHDL中的赋值语句使用`<=`符号。最后，需要使用`&`符号来实现连接操作。