将下面这个Verilog代码转化成VHDL代码“module Tem_Top_tb( ); reg i_clk = 1'b0 ; reg i_rst = 1'b0 ; reg i_ADC_clk ; reg [9:0] i_ADC ; wire o_LED ; wire o_Serial_data; Tem_Top Tem_Top_inst( .i_clk (i_clk ), .i_rst (i_rst ), .i_ADC_clk (i_ADC_clk ), .i_ADC (i_ADC ), .o_LED (o_LED ), .o_Serial_data(o_Serial_data ) ); initial begin i_clk = 0; i_rst = 1; i_ADC_clk = 0; #1000 i_rst = 0; end always #10 i_clk = ~i_clk; always #20 i_ADC_clk = ~i_ADC_clk; reg [19:0] r_cnt = 20'd0; always @(posedge i_ADC_clk)begin if(i_rst == 1'b1) r_cnt <=20'd0; else r_cnt <= r_cnt + 1'b1; end always @(posedge i_ADC_clk)begin case (r_cnt) 20'd200 :i_ADC <= 10'd10 ; 20'd4000 :i_ADC <= 10'd87 ; 20'd15000 :i_ADC <= 10'd108 ; 20'd19500 :i_ADC <= 10'd135 ; 20'd20000 :i_ADC <= 10'd160 ; 20'd40000 :i_ADC <= 10'd115 ; 20'd60000 :i_ADC <= 10'd32 ; 20'd80000 :i_ADC <= 10'd198 ; 20'd100000 :i_ADC <= 10'd248 ; endcase end endmodule”

entity Tem_Top_tb is
end entity;

architecture Behavioral of Tem_Top_tb is
signal i_clk : std_logic := '0';
signal i_rst : std_logic := '0';
signal i_ADC_clk : std_logic;
signal i_ADC : std_logic_vector(9 downto 0);
signal o_LED : std_logic;
signal o_Serial_data : std_logic;
begin

Tem_Top_inst : entity work.Tem_Top
port map (
i_clk => i_clk,
i_rst => i_rst,
i_ADC_clk => i_ADC_clk,
i_ADC => i_ADC,
o_LED => o_LED,
o_Serial_data => o_Serial_data
);

process
begin
i_clk <= '0';
i_rst <= '1';
i_ADC_clk <= '0';
wait for 1000 ns;
i_rst <= '0';
loop
wait for 10 ns;
i_clk <= not i_clk;
end loop;
end process;

process
begin
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait for 20 ns;
i_ADC_clk <= not i_ADC_clk;
wait;
end process;

process
begin
wait until rising_edge(i_ADC_clk);
if i_rst = '1' then
r_cnt <= "00000000000000000000";
else
r_cnt <= r_cnt + 1;
end if;
wait until rising_edge(i_ADC_clk);
case r_cnt is
when 20000 =>
i_ADC <= "0000001010";
when 400000 =>
i_ADC <= "0101010111";
when 1500000 =>
i_ADC <= "0110110100";
when 1950000 =>
i_ADC <= "1000010111";
when 2000000 =>
i_ADC <= "1010000000";
when 4000000 =>
i_ADC <= "0111000111";
when 6000000 =>
i_ADC <= "0010000010";
when 8000000 =>
i_ADC <= "1100011000";
when 10000000 =>
i_ADC <= "11111000";
when others =>
null;
end case;
end process;

end Behavioral;