将这个Verilog顶层文件改成VHDL的格式“module Tem_Top( input i_clk , input i_rst , input i_ADC_clk , input [9:0] i_ADC , output o_LED , output o_Serial_data ); parameter P_AN = 10'sd1 ; parameter P_BN = -10'sd75 ; parameter P_TEMP_MAX = 10'sd75 ; parameter P_TEMP_MIN = -10'sd25 ; parameter P_Device_ID = 4'd7 ; wire w_ADC_valid ; wire [9:0] w_ADC ; Time_sample Time_sample_inst( .i_clk (i_clk ), .i_rst (i_rst ), .i_ADC_clk (i_ADC_clk ), .i_ADC (i_ADC ), .o_ADC_valid (w_ADC_valid ), .o_ADC (w_ADC ) ); wire w_T_valid ; wire signed[13:0] w_T ; Calibration Calibration_inst( .i_clk ( i_clk ), .i_rst ( i_rst ), .i_an ( P_AN ), .i_bn ( P_BN ), .i_sample_valid ( w_ADC_valid ), .i_sample_ADC ( w_ADC ), .o_T_valid ( w_T_valid ), .o_T ( w_T ) ); LED_color #( .P_TEMP_MAX (P_TEMP_MAX ), .P_TEMP_MIN (P_TEMP_MIN ) ) LED_color_inst( .i_clk ( i_clk ), .i_rst ( i_rst ), .i_T_valid ( w_T_valid ), .i_T ( w_T ), .o_LED ( o_LED ) ); Serial_output Serial_output_inst( .i_clk ( i_clk ), .i_rst ( i_rst ), .i_T_valid ( w_T_valid ), .i_T ( w_T ), .i_Device_ID ( P_Device_ID ), .o_Serial_data ( o_Serial_data ) ); endmodule”

entity Tem_Top is
generic (
P_AN: integer := 1;
P_BN: integer := -75;
P_TEMP_MAX: integer := 75;
P_TEMP_MIN: integer := -25;
P_Device_ID: integer := 7
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_ADC_clk : in std_logic;
i_ADC : in std_logic_vector(9 downto 0);
o_LED : out std_logic;
o_Serial_data: out std_logic
);
end entity Tem_Top;

architecture rtl of Tem_Top is
signal w_ADC_valid: std_logic;
signal w_ADC: std_logic_vector(9 downto 0);
signal w_T_valid: std_logic;
signal w_T: signed(13 downto 0);
begin

Time_sample_inst: entity work.Time_sample
port map (
i_clk => i_clk,
i_rst => i_rst,
i_ADC_clk => i_ADC_clk,
i_ADC => i_ADC,
o_ADC_valid => w_ADC_valid,
o_ADC => w_ADC
);

Calibration_inst: entity work.Calibration
port map (
i_clk => i_clk,
i_rst => i_rst,
i_an => P_AN,
i_bn => P_BN,
i_sample_valid=> w_ADC_valid,
i_sample_ADC => w_ADC,
o_T_valid => w_T_valid,
o_T => w_T
);

LED_color_inst: entity work.LED_color
generic map (
P_TEMP_MAX => P_TEMP_MAX,
P_TEMP_MIN => P_TEMP_MIN
)
port map (
i_clk => i_clk,
i_rst => i_rst,
i_T_valid => w_T_valid,
i_T => w_T,
o_LED => o_LED
);

Serial_output_inst: entity work.Serial_output
port map (
i_clk => i_clk,
i_rst => i_rst,
i_T_valid => w_T_valid,
i_T => w_T,
i_Device_ID => P_Device_ID,
o_Serial_data => o_Serial_data
);

end architecture rtl;