讲下面这个Verilog文件转化为VHDL文件“module Serial_output( input i_clk , input i_rst , input i_T_valid , input signed[9:0] i_T , input [3 :0] i_Device_ID , output reg o_Serial_data ); reg Frame_valid = 1'd0 ; reg [13:0] Frame = 13'd0; always @(posedge i_clk)begin if(i_rst == 1'b1)begin Frame_valid <= 1'd0 ; Frame <= 13'd0; end else if(i_T_valid)begin Frame_valid <= 1'b1 ; Frame <= {i_Device_ID,i_T}; end else Frame_valid <= 1'd0 ; end reg [2:0] s_Frame_valid = 3'd0; always @(posedge i_clk)begin s_Frame_valid <= {s_Frame_valid[1:0],Frame_valid}; end reg [4:0] r_bit_cnt = 5'd0; always @(posedge i_clk)begin if(i_rst == 1'b1) r_bit_cnt <= 5'd0; else if(s_Frame_valid[2]) r_bit_cnt <= 5'd0; else if(r_bit_cnt >= 5'd13) r_bit_cnt <= r_bit_cnt; else r_bit_cnt <= r_bit_cnt + 1'b1; end always @(*)begin case (r_bit_cnt) 5'd0 :o_Serial_data <= Frame[13] ; 5'd1 :o_Serial_data <= Frame[12] ; 5'd2 :o_Serial_data <= Frame[11] ; 5'd3 :o_Serial_data <= Frame[10] ; 5'd4 :o_Serial_data <= Frame[9] ; 5'd5 :o_Serial_data <= Frame[8] ; 5'd6 :o_Serial_data <= Frame[7] ; 5'd7 :o_Serial_data <= Frame[6] ; 5'd8 :o_Serial_data <= Frame[5] ; 5'd9 :o_Serial_data <= Frame[4] ; 5'd10 :o_Serial_data <= Frame[3] ; 5'd11 :o_Serial_data <= Frame[2] ; 5'd12 :o_Serial_data <= Frame[1] ; endcase end endmodule”

以下是转化后的VHDL文件：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Serial_output is
    port (
        i_clk         : in  std_logic;
        i_rst         : in  std_logic;
        i_T_valid     : in  std_logic;
        i_T           : in  signed(9 downto 0);
        i_Device_ID   : in  std_logic_vector(3 downto 0);
        o_Serial_data : out std_logic
    );
end entity;

architecture Behavioral of Serial_output is
    signal Frame_valid : std_logic := '0';
    signal Frame       : unsigned(13 downto 0) := (others => '0');
    signal s_Frame_valid : unsigned(2 downto 0) := (others => '0');
    signal r_bit_cnt : unsigned(4 downto 0) := (others => '0');
begin

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            if i_rst = '1' then
                Frame_valid <= '0';
                Frame <= (others => '0');
            elsif i_T_valid = '1' then
                Frame_valid <= '1';
                Frame <= unsigned(i_Device_ID & i_T);
            else
                Frame_valid <= '0';
            end if;
        end if;
    end process;

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            s_Frame_valid <= s_Frame_valid(1 downto 0) & Frame_valid;
        end if;
    end process;

    process (r_bit_cnt)
    begin
        case r_bit_cnt is
            when "00000" =>
                o_Serial_data <= std_logic(Frame(13));
            when "00001" =>
                o_Serial_data <= std_logic(Frame(12));
            when "00010" =>
                o_Serial_data <= std_logic(Frame(11));
            when "00011" =>
                o_Serial_data <= std_logic(Frame(10));
            when "00100" =>
                o_Serial_data <= std_logic(Frame(9));
            when "00101" =>
                o_Serial_data <= std_logic(Frame(8));
            when "00110" =>
                o_Serial_data <= std_logic(Frame(7));
            when "00111" =>
                o_Serial_data <= std_logic(Frame(6));
            when "01000" =>
                o_Serial_data <= std_logic(Frame(5));
            when "01001" =>
                o_Serial_data <= std_logic(Frame(4));
            when "01010" =>
                o_Serial_data <= std_logic(Frame(3));
            when "01011" =>
                o_Serial_data <= std_logic(Frame(2));
            when "01100" =>
                o_Serial_data <= std_logic(Frame(1));
            when others =>
                null;
        end case;
    end process;

    process (i_clk)
    begin
        if rising_edge(i_clk) then
            if i_rst = '1' then
                r_bit_cnt <= (others => '0');
            elsif s_Frame_valid(2) = '1' then
                r_bit_cnt <= (others => '0');
            elsif r_bit_cnt >= 13 then
                r_bit_cnt <= r_bit_cnt;
            else
                r_bit_cnt <= r_bit_cnt + 1;
            end if;
        end if;
    end process;

end architecture;