用verilog语言写一个跑马灯

以下是一个用Verilog语言实现跑马灯的示例代码：

module marquee(
    input clk,
    output reg [7:0] led
);

reg [2:0] count;

always @(posedge clk) begin
    count <= count + 1;
    case (count)
        3'd0: led <= 8'b00000001; // LED 0
        3'd1: led <= 8'b00000010; // LED 1
        3'd2: led <= 8'b00000100; // LED 2
        3'd3: led <= 8'b00001000; // LED 3
        3'd4: led <= 8'b00010000; // LED 4
        3'd5: led <= 8'b00100000; // LED 5
        3'd6: led <= 8'b01000000; // LED 6
        3'd7: led <= 8'b10000000; // LED 7
        default: led <= 8'b00000001; // reset to LED 0
    endcase
end

endmodule

该代码使用一个计数器来控制LED的亮灭，每次计数器加1，然后根据计数器的值选择对应的LED亮起，形成跑马灯的效果。在默认情况下，计数器会在达到最大值后自动重置，以保持循环的效果。