代码: 0x80072F30

错误代码 0x80072F30 是一个 Windows 网络错误代码，表示在与远程服务器建立连接时发生了问题。具体而言，它表示 "The server certificate is invalid"，即服务器证书无效。

这个错误通常出现在使用 HTTPS 协议与远程服务器通信时，可能有以下几个原因导致该错误：

1. 证书过期或无效：服务器的证书可能已过期或被吊销，或者存在其他问题导致无法验证该证书的有效性。

2. 证书链不完整：服务器证书链中的某个中间证书可能缺失或无效。

3. 证书主机名不匹配：服务器的证书主机名与实际连接的主机名不匹配，可能是由于 DNS 配置错误或服务器配置问题造成的。

解决这个问题的方法可以有以下几个步骤：

1. 检查系统时间和日期：确保系统时间和日期设置正确，因为证书验证通常依赖于正确的时间戳。

2. 更新操作系统及浏览器：确保你的操作系统和浏览器是最新版本，并且已经安装了最新的安全更新。

3. 清除缓存和临时文件：清除浏览器缓存和临时文件，以确保不会因为过期或损坏的缓存数据导致问题。

4. 检查网络连接及防火墙设置：确保你的网络连接正常，并且没有被防火墙或代理服务器阻止访问远程服务器。

如果以上方法都没有解决问题，那么可能需要联系网站管理员或网络服务提供商，以获取更多帮助和支持。

相关问题

gd32f30x配置Enet接口示例代码

以下是一份gd32f30x配置Enet接口的示例代码，仅供参考：

#include "gd32f30x.h"

#define ETH_MAC_ADDR0   (0x00)
#define ETH_MAC_ADDR1   (0x80)
#define ETH_MAC_ADDR2   (0xE1)
#define ETH_MAC_ADDR3   (0x00)
#define ETH_MAC_ADDR4   (0x00)
#define ETH_MAC_ADDR5   (0x01)

__IO uint32_t  EthStatus = 0;
uint8_t MACAddr[6] = {ETH_MAC_ADDR0, ETH_MAC_ADDR1, ETH_MAC_ADDR2, ETH_MAC_ADDR3, ETH_MAC_ADDR4, ETH_MAC_ADDR5};

void ETH_GPIO_Config(void);
void ETH_MACDMA_Config(void);
void ETH_NVIC_Config(void);
void ETH_MACDMAInit(void);
void ETH_DMARxDescChainInit(void);
void ETH_DMATxDescChainInit(void);
void ETH_RxPkt_ChainMode(void);
void ETH_TxPkt_ChainMode(void);

int main(void)
{
    /* configure ethernet GPIO */
    ETH_GPIO_Config();
    /* configure ethernet MAC/DMA */
    ETH_MACDMA_Config();
    /* configure ethernet NVIC */
    ETH_NVIC_Config();
    /* initialize ethernet MAC/DMA */
    ETH_MACDMAInit();
    /* initialize ethernet Rx descriptors */
    ETH_DMARxDescChainInit();
    /* initialize ethernet Tx descriptors */
    ETH_DMATxDescChainInit();
    /* receive packet in chain mode */
    ETH_RxPkt_ChainMode();
    /* transmit packet in chain mode */
    ETH_TxPkt_ChainMode();

    while(1){}
}

/**
  * @brief  configure ethernet GPIO
  * @param  None
  * @retval None
  */
void ETH_GPIO_Config(void)
{
    /* enable ethernet GPIO clocks */
    rcu_periph_clock_enable(RCU_GPIOA);
    rcu_periph_clock_enable(RCU_GPIOC);
    rcu_periph_clock_enable(RCU_AF);

    /* config ethernet pins (PA2/PA3/PA7/PC1/PC4/PC5) */
    gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_7);
    gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
}

/**
  * @brief  configure ethernet MAC/DMA
  * @param  None
  * @retval None
  */
void ETH_MACDMA_Config(void)
{
    /* enable ethernet MAC/DMA clocks */
    rcu_periph_clock_enable(RCU_ETHMAC);
    rcu_periph_clock_enable(RCU_DMA0);

    /* reset ethernet MAC/DMA */
    rcu_periph_reset_enable(RCU_ETHMAC);
    rcu_periph_reset_enable(RCU_DMA0);
    rcu_periph_reset_disable(RCU_ETHMAC);
    rcu_periph_reset_disable(RCU_DMA0);

    /* select MII interface mode */
    ETH_MACInterfaceModeConfig(ETH_MAC_INTERFACE_MODE_MII);

    /* configure ethernet MAC */
    ETH_MACInitTypeDef MACInit;
    MACInit.watchdog = ETH_WATCHDOG_ENABLE;
    MACInit.jabber = ETH_JABBER_ENABLE;
    MACInit.inter_frame_gap = ETH_INTER_FRAME_GAP_96BITS;
    MACInit.checksum_offload = ETH_CHECKSUM_OFFLOAD_ENABLE;
    MACInit.retry_transmission = ETH_RETRY_TRANSMISSION_DISABLE;
    MACInit.auto_negotiation = ETH_AUTO_NEGOTIATION_DISABLE;
    MACInit.power_down = ETH_POWER_DOWN_DISABLE;
    MACInit.loopback_mode = ETH_LOOPBACK_MODE_DISABLE;
    MACInit.duplex_mode = ETH_MODE_FULLDUPLEX;
    MACInit.speed = ETH_SPEED_100M;
    ETH_MACInit(&MACInit, MACAddr);

    /* configure ethernet DMA */
    ETH_DMATxInitTypeDef DMAInitTx;
    DMAInitTx.dma_tx_queue = ETH_DMA_TX_QUEUE_0;
    DMAInitTx.dma_tx_desc_segments = ETH_DMA_TX_SEGMENTS_1;
    DMAInitTx.dma_tx_desc_size = ETH_DMA_TX_DESC_SIZE;
    DMAInitTx.dma_tx_desc_addr = (uint32_t)tx_desc;
    ETH_DMATxInit(&DMAInitTx);

    ETH_DMARxInitTypeDef DMAInitRx;
    DMAInitRx.dma_rx_queue = ETH_DMA_RX_QUEUE_0;
    DMAInitRx.dma_rx_desc_segments = ETH_DMA_RX_SEGMENTS_1;
    DMAInitRx.dma_rx_desc_size = ETH_DMA_RX_DESC_SIZE;
    DMAInitRx.dma_rx_desc_addr = (uint32_t)rx_desc;
    ETH_DMARxInit(&DMAInitRx);
}

/**
  * @brief  configure ethernet NVIC
  * @param  None
  * @retval None
  */
void ETH_NVIC_Config(void)
{
    nvic_irq_enable(ETH_IRQn, 0, 0);
}

/**
  * @brief  initialize ethernet MAC/DMA
  * @param  None
  * @retval None
  */
void ETH_MACDMAInit(void)
{
    ETH_Start();
    ETH_DMATxEnable(ETH_DMA_TX_QUEUE_0);
    ETH_DMARxEnable(ETH_DMA_RX_QUEUE_0);
}

/**
  * @brief  initialize ethernet Rx descriptors
  * @param  None
  * @retval None
  */
void ETH_DMARxDescChainInit(void)
{
    /* set Rx descriptors to zero */
    memset(rx_desc, 0, sizeof(rx_desc));

    /* Initialize Rx descriptors in chain mode */
    for (int i = 0; i < ETH_DMA_RX_DESC_COUNT; i++) {
        rx_desc[i].status |= ETH_DMARXDESC_OWN;
        rx_desc[i].status &= ~(ETH_DMARXDESC_LS | ETH_DMARXDESC_FS);
        rx_desc[i].basic.status = ETH_DMARXDESC_OWN;
        rx_desc[i].basic.status |= ETH_DMARXDESC_BUF1V;
        rx_desc[i].basic.length = ETH_RX_BUF_SIZE;
        rx_desc[i].basic.buf1_addr = (uint32_t)rx_buf[i];
        if (i == (ETH_DMA_RX_DESC_COUNT - 1)) {
            rx_desc[i].basic.status |= ETH_DMARXDESC_EOP;
        }
        rx_desc[i].next = (uint32_t)&rx_desc[i+1];
    }

    /* set last descriptor with wrap flag */
    rx_desc[ETH_DMA_RX_DESC_COUNT-1].basic.status |= ETH_DMARXDESC_WRAP;
    rx_desc[ETH_DMA_RX_DESC_COUNT-1].next = (uint32_t)rx_desc;
    ETH_DMARxDescListInit(rx_desc, ETH_DMA_RX_DESC_COUNT);
}

/**
  * @brief  initialize ethernet Tx descriptors
  * @param  None
  * @retval None
  */
void ETH_DMATxDescChainInit(void)
{
    /* set Tx descriptors to zero */
    memset(tx_desc, 0, sizeof(tx_desc));

    /* Initialize Tx descriptors in chain mode */
    for (int i = 0; i < ETH_DMA_TX_DESC_COUNT; i++) {
        tx_desc[i].status |= ETH_DMATXDESC_OWN;
        tx_desc[i].status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS | ETH_DMATXDESC_IC | ETH_DMATXDESC_DC);
        tx_desc[i].basic.status = ETH_DMATXDESC_OWN;
        tx_desc[i].basic.status |= ETH_DMATXDESC_BUF1V;
        if (i == (ETH_DMA_TX_DESC_COUNT - 1)) {
            tx_desc[i].basic.status |= ETH_DMATXDESC_EOP;
        }
        tx_desc[i].basic.length = ETH_TX_BUF_SIZE;
        tx_desc[i].basic.buf1_addr = (uint32_t)tx_buf[i];
        tx_desc[i].next = (uint32_t)&tx_desc[i+1];
    }

    /* set last descriptor with wrap flag */
    tx_desc[ETH_DMA_TX_DESC_COUNT-1].basic.status |= ETH_DMATXDESC_WRAP;
    tx_desc[ETH_DMA_TX_DESC_COUNT-1].next = (uint32_t)tx_desc;
    ETH_DMATxDescListInit(tx_desc, ETH_DMA_TX_DESC_COUNT);
}

/**
  * @brief  receive packet in chain mode
  * @param  None
  * @retval None
  */
void ETH_RxPkt_ChainMode(void)
{
    uint32_t framelength = 0;
    uint32_t ethDestAddr[2];
    uint32_t ethSrcAddr[2];
    uint16_t ethType;

    if ((rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) {
        if ((rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status & ETH_DMARXDESC_ES) == (uint32_t)RESET) {
            framelength = ((rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status & ETH_DMARXDESC_FL) >> 16) & 0x3FFF;
            ethDestAddr[0] = rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.buf1_addr;
            ethDestAddr[1] = rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.buf2_addr;
            ethSrcAddr[0] = rx_desc[ETH_DMA_RX_CURR_DESC_IDX].extended.status & 0xFFFF;
            ethSrcAddr[1] = rx_desc[ETH_DMA_RX_CURR_DESC_IDX].extended.buf1_addr;

            /* check ethernet packet type */
            ethType = (uint16_t)(*(uint32_t *)(rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.buf1_addr + 12));
            if (ethType == 0x0800) { /* IPv4 */
                /* process IPv4 packet */
            } else if (ethType == 0x86DD) { /* IPv6 */
                /* process IPv6 packet */
            }

            rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status = ETH_DMARXDESC_OWN;
            rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status |= ETH_DMARXDESC_BUF1V;
            rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.length = ETH_RX_BUF_SIZE;
            rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.buf1_addr = (uint32_t)rx_buf[ETH_DMA_RX_CURR_DESC_IDX];
            if (ETH_DMA_RX_CURR_DESC_IDX == (ETH_DMA_RX_DESC_COUNT - 1)) {
                rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status |= ETH_DMARXDESC_EOP;
            }
            if ((ETH_DMA_RX_CURR_DESC_IDX % 2) == 0) {
                rx_desc[ETH_DMA_RX_CURR_DESC_IDX].basic.status |= ETH_DMARXDESC_FS;
            }
            rx_desc[ETH_DMA_RX_CURR_DESC_IDX].next = (uint32_t)&rx_desc[ETH_DMA_RX_CURR_DESC_IDX+1];
            ETH_DMA_RX_CURR_DESC_IDX = (ETH_DMA_RX_CURR_DESC_IDX + 1) % ETH_DMA_RX_DESC_COUNT;
        }
    }
}

/**
  * @brief  transmit packet in chain mode
  * @param  None
  * @retval None
  */
void ETH_TxPkt_ChainMode(void)
{
    /* fill Tx buffer with data to transmit */
    memset(tx_buf[ETH_DMA_TX_CURR_DESC_IDX], 0, ETH_TX_BUF_SIZE);
    memcpy(tx_buf[ETH_DMA_TX_CURR_DESC_IDX], "Hello world!", 12);

    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status = ETH_DMATXDESC_OWN;
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status |= ETH_DMATXDESC_BUF1V;
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.length = 12;
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.buf1_addr = (uint32_t)tx_buf[ETH_DMA_TX_CURR_DESC_IDX];
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status |= ETH_DMATXDESC_LS;
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status |= ETH_DMATXDESC_FS;
    tx_desc[ETH_DMA_TX_CURR_DESC_IDX].next = (uint32_t)&tx_desc[ETH_DMA_TX_CURR_DESC_IDX+1];
    if (ETH_DMA_TX_CURR_DESC_IDX == (ETH_DMA_TX_DESC_COUNT - 1)) {
        tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status |= ETH_DMATXDESC_EOP;
        tx_desc[ETH_DMA_TX_CURR_DESC_IDX].basic.status |= ETH_DMATXDESC_IC;
    }
    ETH_DMA_TX_CURR_DESC_IDX = (ETH_DMA_TX_CURR_DESC_IDX + 1) % ETH_DMA_TX_DESC_COUNT;
    ETH_DMATxDescListInit(tx_desc, ETH_DMA_TX_DESC_COUNT);
    ETH_DMATxEnable(ETH_DMA_TX_QUEUE_0);
}

该示例代码的具体实现细节可以参考GD32F30x固件库的官方文档，也可以根据需要进行修改。

sm3算法python代码实现

以下是Python中实现sm3算法的代码示例：

import struct
import hashlib

class SM3Hash:
    def __init__(self):
        self.iv = [0x7380166F, 0x4914B2B9, 0x172442D7, 0xDA8A0600, 0xA96F30BC, 0x163138AA, 0xE38DEE4D, 0xB0FB0E4E]
        self.tj = []
        for i in range(0, 16):
            self.tj.append(0x79CC4519)
        for i in range(16, 64):
            self.tj.append(0x7A879D8A)
        self.A, self.B, self.C, self.D, self.E, self.F, self.G, self.H = self.iv[0], self.iv[1], self.iv[2], self.iv[3], self.iv[4], self.iv[5], self.iv[6], self.iv[7]

    def _CF(self, X):
        W = []
        for i in range(0, 16):
            W.append(X[i])
        for i in range(16, 68):
            W.append(self._P1(W[i-16] ^ W[i-9] ^ (self._ROTATE_LEFT(W[i-3], 15))) ^ (self._ROTATE_LEFT(W[i-13], 7)) ^ W[i-6])
        for i in range(68, 64):
            W.append(self._P1(W[i-16] ^ W[i-9] ^ (self._ROTATE_LEFT(W[i-3], 15))) ^ (self._ROTATE_LEFT(W[i-13], 7)) ^ W[i-6] ^ W[i-64])
        A, B, C, D, E, F, G, H = self.A, self.B, self.C, self.D, self.E, self.F, self.G, self.H
        for i in range(0, 64):
            SS1 = self._ROTATE_LEFT((self._ROTATE_LEFT(A, 12) + E + self._ROTATE_LEFT(self.tj[i], i % 32)) & 0xFFFFFFFF, 7)
            SS2 = SS1 ^ self._ROTATE_LEFT(A, 12)
            TT1 = (self._FFj(A, B, C, i) + D + SS2 + W[i]) & 0xFFFFFFFF
            TT2 = (self._GGj(E, F, G, i) + H + SS1 + W[i]) & 0xFFFFFFFF
            D = C
            C = self._ROTATE_LEFT(B, 9)
            B = A
            A = TT1
            H = G
            G = self._ROTATE_LEFT(F, 19)
            F = E
            E = self._P0(TT2)
        self.A = (self.A + A) & 0xFFFFFFFF
        self.B = (self.B + B) & 0xFFFFFFFF
        self.C = (self.C + C) & 0xFFFFFFFF
        self.D = (self.D + D) & 0xFFFFFFFF
        self.E = (self.E + E) & 0xFFFFFFFF
        self.F = (self.F + F) & 0xFFFFFFFF
        self.G = (self.G + G) & 0xFFFFFFFF
        self.H = (self.H + H) & 0xFFFFFFFF

    def _P0(self, X):
        return X ^ self._ROTATE_LEFT(X, 9) ^ self._ROTATE_LEFT(X, 17)

    def _P1(self, X):
        return X ^ self._ROTATE_LEFT(X, 15) ^ self._ROTATE_LEFT(X, 23)

    def _FFj(self, X, Y, Z, j):
        if j >= 0 and j <= 15:
            return X ^ Y ^ Z
        else:
            return (X & Y) | (X & Z) | (Y & Z)

    def _GGj(self, X, Y, Z, j):
        if j >= 0 and j <= 15:
            return X ^ Y ^ Z
        else:
            return (X & Y) | (~X & Z)

    def _ROTATE_LEFT(self, x, n):
        return (((x) << (n)) & 0xFFFFFFFF) | ((x) >> (32-(n)))

    def _padding(self, data):
        length = len(data) * 8
        data += b'\x80'
        data += b'\x00' * (((56 - (length + 8) % 64) % 64) - 1)
        data += struct.pack('>Q', length)
        return data

    def update(self, data):
        data = self._padding(data)
        for i in range(0, len(data), 64):
            block = data[i:i+64]
            X = []
            for j in range(0, 16):
                X.append(struct.unpack('>I', block[j*4:j*4+4])[0])
            self._CF(X)

    def digest(self):
        return struct.pack('>IIIIIIII', self.A, self.B, self.C, self.D, self.E, self.F, self.G, self.H)

    def hexdigest(self):
        return self.digest().hex()

def sm3(data):
    h = SM3Hash()
    h.update(data)
    return h.hexdigest()

message = b'This is a test message.'
hash_value = sm3(message)
print(hash_value)

需要注意的是，在使用时需要将待哈希的数据转换为字节串传入`sm3`函数中。另外，在实现过程中，需要使用一些位运算的技巧，详情请参考SM3算法的相关文献。