帮我写一段FIFO的Verilog代码

以下是FIFO的Verilog代码：

module fifo (
input clk,
input reset,
input write_enable,
input read_enable,
input [7:0] data_in,
output [7:0] data_out,
output full,
output empty);

parameter WIDTH = 8; // 数据宽度
parameter DEPTH = 16; // 队列深度

reg [WIDTH-1:0] memory [DEPTH-1:0];
reg [DEPTH-1:0] read_pointer;
reg [DEPTH-1:0] write_pointer;
wire [DEPTH-1:0] used_space;
wire [DEPTH-1:0] free_space;

assign full = (used_space == DEPTH);
assign empty = (used_space == 0);

assign data_out = memory[read_pointer];

assign free_space = DEPTH - used_space;

always @ (posedge clk) begin
if (reset) begin
read_pointer <= 0;
write_pointer <= 0;
end else begin
if (read_enable && !empty) begin
read_pointer <= read_pointer + 1;
end
if (write_enable && !full) begin
memory[write_pointer] <= data_in;
write_pointer <= write_pointer + 1;
end
end
end

assign used_space = write_pointer - read_pointer;

endmodule

本代码实现了一个带有读写使能的FIFO队列，有16个存储位置，每个位置存储8位数据。队列满时full信号为1，队列空时empty信号为1。本代码使用了两个指针read_pointer和write_pointer，用于指示读写位置。在时钟上升沿时，根据读写使能信号和队列状态更新指针和数据存储。