数字电路数码管倒计时VHDL源代码

以下是数字电路数码管倒计时的VHDL源代码示例：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity countdown is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           count_start : in  STD_LOGIC;
           digit_out : out  STD_LOGIC_VECTOR (3 downto 0));
end countdown;

architecture Behavioral of countdown is

    signal count : integer range 0 to 9 := 0;
    signal timer : integer range 0 to 9999 := 0;
    signal count_en : std_logic := '0';
    signal display : std_logic_vector(3 downto 0);

begin

    process (clk, reset)
    begin
        if reset = '1' then
            count <= 0;
            timer <= 0;
            count_en <= '0';
            display <= "0000";
        elsif (rising_edge(clk)) then
            if count_start = '1' then
                count_en <= '1';
            end if;
            if count_en = '1' then
                timer <= timer + 1;
                if timer = 10000 then
                    count <= count + 1;
                    timer <= 0;
                end if;
                if count = 10 then
                    count <= 0;
                    count_en <= '0';
                end if;
            end if;
        end if;
    end process;

    process (count)
    begin
        case count is
            when 0 => display <= "11111100"; -- 0
            when 1 => display <= "01100000"; -- 1
            when 2 => display <= "11011010"; -- 2
            when 3 => display <= "11110010"; -- 3
            when 4 => display <= "01100110"; -- 4
            when 5 => display <= "10110110"; -- 5
            when 6 => display <= "10111110"; -- 6
            when 7 => display <= "11100000"; -- 7
            when 8 => display <= "11111110"; -- 8
            when 9 => display <= "11110110"; -- 9
        end case;
    end process;

    digit_out <= display;

end Behavioral;

该代码实现了一个基于时钟和重置信号的倒计时器，当计数开始信号count_start为高电平时，数字会从9开始倒数到0。在此过程中，数字通过4位数码管显示。