VHDL实现数码管

下面是一个简单的 VHDL 代码实现数码管的例子：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seven_segment_display is
    Port ( clk : in  STD_LOGIC;
           num : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (6 downto 0));
end seven_segment_display;

architecture Behavioral of seven_segment_display is
begin
    process (clk)
    begin
        if (rising_edge(clk)) then
            case num is
                when "0000" => seg <= "0000001"; --0
                when "0001" => seg <= "1001111"; --1
                when "0010" => seg <= "0010010"; --2
                when "0011" => seg <= "0000110"; --3
                when "0100" => seg <= "1001100"; --4
                when "0101" => seg <= "0100100"; --5
                when "0110" => seg <= "0100000"; --6
                when "0111" => seg <= "0001111"; --7
                when "1000" => seg <= "0000000"; --8
                when "1001" => seg <= "0001100"; --9
                when others => seg <= "1111111"; --invalid input
            end case;
        end if;
    end process;
end Behavioral;

这段代码实现了一个四位数码管，输入为四位二进制数，输出为七位二进制数，代表对应数字在数码管上的显示。在代码中，使用了一个时钟信号 clk 进行同步，并通过一个 case 语句对输入数字进行判断，并输出对应的七位二进制数。