UART接收模块的代码及用来仿真的测试代码，要求里面包括FIFO和状态机

好的，下面是一个基于FIFO和状态机的UART接收模块的代码及测试代码：

UART接收模块代码：

module uart_rx_module(
  input clk,
  input reset,
  input rx,
  output reg [7:0] data_out,
  output reg data_ready
);

  // 定义状态机状态
  parameter IDLE = 2'b00;
  parameter START = 2'b01;
  parameter DATA = 2'b10;
  parameter STOP = 2'b11;
  
  // 定义状态机信号
  reg [1:0] state = IDLE;
  reg [7:0] data_reg;
  reg [3:0] fifo [0:15];
  reg [3:0] write_ptr = 0;
  reg [3:0] read_ptr = 0;
  reg [3:0] fifo_count = 0;
  
  // 状态机
  always @(posedge clk) begin
    case(state)
      IDLE: begin
        if(rx == 0) begin
          state <= START;
        end
      end
      START: begin
        data_reg <= 8'b00000000;
        state <= DATA;
      end
      DATA: begin
        data_reg <= {data_reg[6:0], rx};
        if(fifo_count < 16) begin
          fifo[write_ptr] <= data_reg;
          write_ptr <= write_ptr + 1;
          fifo_count <= fifo_count + 1;
        end
        if(fifo_count == 16) begin
          state <= STOP;
        end
      end
      STOP: begin
        data_ready <= 1;
        state <= IDLE;
      end
    endcase
  end
  
  // FIFO
  always @(posedge clk) begin
    if(reset == 1) begin
      write_ptr <= 0;
      read_ptr <= 0;
      fifo_count <= 0;
    end else begin
      if(fifo_count > 0) begin
        read_ptr <= read_ptr + 1;
        fifo_count <= fifo_count - 1;
      end
    end
  end
  
  // 输出
  always @(posedge clk) begin
    if(reset == 1) begin
      data_out <= 0;
      data_ready <= 0;
    end else begin
      if(fifo_count > 0) begin
        data_out <= fifo[read_ptr];
        data_ready <= 0;
      end else begin
        data_ready <= 1;
      end
    end
  end

endmodule

测试代码：

module uart_rx_module_test();

  // 时钟信号
  reg clk;
  always #5 clk = ~clk;
  
  // 输入信号
  reg reset;
  reg rx;
  
  // 输出信号
  wire [7:0] data_out;
  wire data_ready;
  
  // 实例化模块
  uart_rx_module uart_rx(
    .clk(clk),
    .reset(reset),
    .rx(rx),
    .data_out(data_out),
    .data_ready(data_ready)
  );
  
  // 初始化
  initial begin
    clk = 0;
    reset = 1;
    rx = 1;
    #10 reset = 0;
  end
  
  // 发送数据
  integer i;
  initial begin
    rx = 0;
    #20 rx = 1;
    for(i = 0; i < 16; i = i + 1) begin
      #10 rx = $random;
    end
    #100 $finish;
  end
  
  // 输出结果
  always @(posedge clk) begin
    if(data_ready == 1) begin
      $display("data_out = %d", data_out);
    end
  end

endmodule