四路抢答器verilog

以下是一个简单的四路抢答器的 Verilog 代码：

module four_way_arbiter (
    input clk,
    input [3:0] req,
    output reg [3:0] grant
);

reg [3:0] req_reg;
reg [1:0] winner;

always @(posedge clk) begin
    req_reg <= req;
    if (req_reg[0] && !req_reg[1] && !req_reg[2] && !req_reg[3]) begin
        winner <= 2'b00;
        grant <= 4'b0001;
    end
    else if (!req_reg[0] && req_reg[1] && !req_reg[2] && !req_reg[3]) begin
        winner <= 2'b01;
        grant <= 4'b0010;
    end
    else if (!req_reg[0] && !req_reg[1] && req_reg[2] && !req_reg[3]) begin
        winner <= 2'b10;
        grant <= 4'b0100;
    end
    else if (!req_reg[0] && !req_reg[1] && !req_reg[2] && req_reg[3]) begin
        winner <= 2'b11;
        grant <= 4'b1000;
    end
    else if (winner == 2'b00 && req_reg[1]) begin
        winner <= 2'b01;
        grant <= 4'b0010;
    end
    else if (winner == 2'b00 && req_reg[2]) begin
        winner <= 2'b10;
        grant <= 4'b0100;
    end
    else if (winner == 2'b00 && req_reg[3]) begin
        winner <= 2'b11;
        grant <= 4'b1000;
    end
    else if (winner == 2'b01 && req_reg[0]) begin
        winner <= 2'b00;
        grant <= 4'b0001;
    end
    else if (winner == 2'b01 && req_reg[2]) begin
        winner <= 2'b10;
        grant <= 4'b0100;
    end
    else if (winner == 2'b01 && req_reg[3]) begin
        winner <= 2'b11;
        grant <= 4'b1000;
    end
    else if (winner == 2'b10 && req_reg[0]) begin
        winner <= 2'b00;
        grant <= 4'b0001;
    end
    else if (winner == 2'b10 && req_reg[1]) begin
        winner <= 2'b01;
        grant <= 4'b0010;
    end
    else if (winner == 2'b10 && req_reg[3]) begin
        winner <= 2'b11;
        grant <= 4'b1000;
    end
    else if (winner == 2'b11 && req_reg[0]) begin
        winner <= 2'b00;
        grant <= 4'b0001;
    end
    else if (winner == 2'b11 && req_reg[1]) begin
        winner <= 2'b01;
        grant <= 4'b0010;
    end
    else if (winner == 2'b11 && req_reg[2]) begin
        winner <= 2'b10;
        grant <= 4'b0100;
    end
end

endmodule

这个模块有两个输入，一个时钟信号 `clk` 和一个四位二进制向量 `req`，表示四个请求信号。输出是一个四位二进制向量 `grant`，表示哪个请求信号被授予，每个比特位对应一个请求信号。