写段复杂得verilog得testbench

以下是一个比较复杂的Verilog testbench示例，用于测试一个简单的16位ALU模块，该模块包括加、减、与、或等操作。

`timescale 1ns/1ns

module alu_tb;

// Inputs
reg [15:0] a, b;
reg [3:0] op;

// Outputs
wire [15:0] result;

// Instantiate the DUT
alu dut(.a(a), .b(b), .op(op), .result(result));

// Clock
reg clk = 0;

// Run the clock
always
    #5 clk = ~clk;

// Test cases
initial begin
    // Add operation
    op = 4'b0000;
    a = 16'h1234;
    b = 16'h5678;
    #10;
    if(result !== 16'h68AC) $display("Test case 1 failed");

    // Subtract operation
    op = 4'b0001;
    a = 16'h5678;
    b = 16'h1234;
    #10;
    if(result !== 16'h4444) $display("Test case 2 failed");

    // And operation
    op = 4'b0010;
    a = 16'hAAAA;
    b = 16'h5555;
    #10;
    if(result !== 16'h0000) $display("Test case 3 failed");

    // Or operation
    op = 4'b0011;
    a = 16'hAAAA;
    b = 16'h5555;
    #10;
    if(result !== 16'hFFFF) $display("Test case 4 failed");

    // Xor operation
    op = 4'b0100;
    a = 16'hAAAA;
    b = 16'h5555;
    #10;
    if(result !== 16'hAAAA) $display("Test case 5 failed");

    // Shift left operation
    op = 4'b0101;
    a = 16'h1234;
    b = 5;
    #10;
    if(result !== 16'h2468) $display("Test case 6 failed");

    // Shift right operation
    op = 4'b0110;
    a = 16'h1234;
    b = 5;
    #10;
    if(result !== 16'h0489) $display("Test case 7 failed");

    // Arithmetic shift right operation
    op = 4'b0111;
    a = 16'h8000;
    b = 1;
    #10;
    if(result !== 16'hC000) $display("Test case 8 failed");

    // Rotate left operation
    op = 4'b1000;
    a = 16'h1234;
    b = 4;
    #10;
    if(result !== 16'h2341) $display("Test case 9 failed");

    // Rotate right operation
    op = 4'b1001;
    a = 16'h1234;
    b = 4;
    #10;
    if(result !== 16'h4123) $display("Test case 10 failed");

    // Overflow test
    op = 4'b0000;
    a = 16'h7FFF;
    b = 16'h0001;
    #10;
    if(result !== 16'h8000) $display("Test case 11 failed");

    $display("All test cases passed");
    $finish;
end

endmodule

该testbench包括一个时钟生成器、一个ALU模块的实例化、多个测试用例以及一个判断所有测试用例是否通过的语句。每个测试用例都包括对输入信号的设置、等待一段时间、以及对输出结果的检查。如果某个测试用例失败，会输出一个错误信息并终止仿真。