用verilog代码写一个数字时钟

下面是一个使用 Verilog 语言编写的数字时钟的代码示例：

module digital_clock(
  input clk,
  output reg [3:0] hour,
  output reg [3:0] minute,
  output reg [3:0] second
);

reg [3:0] count_second = 0;
reg [3:0] count_minute = 0;
reg [3:0] count_hour = 0;

always @(posedge clk) begin
  count_second <= count_second + 1;
  if (count_second == 10) begin
    count_second <= 0;
    count_minute <= count_minute + 1;
  end
  if (count_minute == 6) begin
    count_minute <= 0;
    count_hour <= count_hour + 1;
  end
  if (count_hour == 10) begin
    count_hour <= 0;
  end
  second <= count_second;
  minute <= count_minute;
  hour <= count_hour;
end

endmodule

这个模块包含三个输出端口，分别表示小时、分钟和秒钟。时钟信号 `clk` 作为输入端口。计数器变量 `count_second`、`count_minute` 和 `count_hour` 用于记录当前的秒、分和小时数。在时钟上升沿时，计数器变量递增。当计数器达到上限时，会发出一个进位信号，进而更新较高位的计数器。最后，小时、分钟和秒钟输出端口会被更新为计数器变量的值。这样，数字时钟就实现了。