写一下这段代码的tb文件：module div_clk(clk,fs,cko); input clk; //输入时钟频率clk=50M input [31:0]fs; output cko; //输出时钟cko reg cko; parameter N=50_000_000; //定义累加器上限，需要与基准频率f0相等 reg [31:0]ACC; //定义32位累加器ACC always @(posedge clk) begin //累加器在clk上升沿触发完成累加 if(ACC<N/2-1) ACC = ACC + fs; //累加器按参数步进值累加，注意不是+1 else begin //满足累加器溢出条件 ACC=0; cko=!cko; //这里cko自身二分频，所以上一句N需要除以2 end end endmodule

以下是一个简单的div_clk模块的tb文件示例：

`timescale 1ns/1ns

module div_clk_tb;

  // Inputs
  reg clk;
  reg [31:0] fs;

  // Outputs
  wire cko;

  // Instantiate the Unit Under Test (UUT)
  div_clk uut (
    .clk(clk), 
    .fs(fs), 
    .cko(cko)
  );

  initial begin
    // Initialize Inputs
    clk = 0;
    fs = 100_000; // Example input value

    #10; // Wait for 10ns before starting the test

    // Test case 1: Verify that cko is low initially
    if (cko !== 0) begin
      $error("Test case 1 failed: cko should be low initially");
    end

    // Test case 2: Verify that cko toggles after fs/2 cycles of clk
    #((fs/2)*20); // Wait for fs/2 cycles of clk
    if (cko !== 1) begin
      $error("Test case 2 failed: cko should be high after fs/2 cycles of clk");
    end
    #((fs/2)*20); // Wait for another fs/2 cycles of clk
    if (cko !== 0) begin
      $error("Test case 2 failed: cko should be low after another fs/2 cycles of clk");
    end

    $display("All test cases passed.");
    $finish;
  end

  always #10 clk = ~clk; // Toggle clk every 10ns

endmodule

该tb文件使用时钟频率为50MHz和输入时钟步进值fs作为输入，输出时钟频率cko。它实例化了div_clk模块，并通过两个测试用例验证了其功能。其中第一个测试用例验证了在模块启动时cko是否为低电平，第二个测试用例验证了在fs/2个时钟周期后cko是否会切换状态。