用quartus verilog语言写一个或非门实验，

module or_gate(input a, input b, output y);
assign y = a | b;
endmodule

// 测试代码
module test_or_gate;
reg a, b;
wire y;

or_gate UUT(a, b, y);

initial begin
a = 0; b = 0;
#10;
if(y !== 0) $display("Test failed: a=%d, b=%d, y=%d", a, b, y);
a = 0; b = 1;
#10;
if(y !== 1) $display("Test failed: a=%d, b=%d, y=%d", a, b, y);
a = 1; b = 0;
#10;
if(y !== 1) $display("Test failed: a=%d, b=%d, y=%d", a, b, y);
a = 1; b = 1;
#10;
if(y !== 1) $display("Test failed: a=%d, b=%d, y=%d", a, b, y);
end
endmodule