用状态机实现101101的序列检测模块，a为输入端，b为输出端，如果检测到a连续输入101101，则b输出脉冲1，否则输出0。请用RTL实现。

以下是 RTL (硬件描述语言) 的代码实现：

module seq_detect (a, b);
   input a;
   output b;
   reg b;
   reg [2:0] state;
   parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011;
   parameter S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
   always @ (a or state) begin
      case (state)
         S0: if (a) state = S1; else state = S0;
         S1: if (a) state = S2; else state = S0;
         S2: if (a) state = S3; else state = S0;
         S3: if (a) state = S4; else state = S0;
         S4: if (a) state = S5; else state = S0;
         S5: if (a) state = S6; else state = S0;
         S6: if (a) state = S7; else state = S0;
         S7: if (a) state = S7; else state = S0;
         default: state = S0;
      endcase
      if (state == S7) b = 1'b1; else b = 1'b0;
   end
endmodule

这段代码实现了一个状态机，可以检测输入端 a 上是否连续输入了101101序列。如果检测到，则输出端 b 输出脉冲1；否则，输出0。