给出真值表，写一段用到CASE语句的VHDL语言

以下是一个四输入逻辑门的真值表：

| A | B | C | D | OUT |
|---|---|---|---|-----|
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |

下面是相应的VHDL代码：

library ieee;
use ieee.std_logic_1164.all;

entity four_input_logic_gate is
  port (
    A, B, C, D : in  std_logic;
    OUT       : out std_logic
  );
end four_input_logic_gate;

architecture rtl of four_input_logic_gate is
begin
  process (A, B, C, D)
  begin
    case (A & B & C & D) is
      when "0000" =>
        OUT <= '1';
      when "0001" =>
        OUT <= '0';
      when "0010" =>
        OUT <= '0';
      when "0011" =>
        OUT <= '1';
      when "0100" =>
        OUT <= '0';
      when "0101" =>
        OUT <= '1';
      when "0110" =>
        OUT <= '1';
      when "0111" =>
        OUT <= '0';
      when "1000" =>
        OUT <= '0';
      when "1001" =>
        OUT <= '1';
      when "1010" =>
        OUT <= '1';
      when "1011" =>
        OUT <= '0';
      when "1100" =>
        OUT <= '1';
      when "1101" =>
        OUT <= '0';
      when "1110" =>
        OUT <= '0';
      when "1111" =>
        OUT <= '1';
    end case;
  end process;
end rtl;

这段代码中，我们使用了一个process块，来响应输入的变化。在process块中，我们使用了`case`语句，对输入进行判断，并根据真值表的结果来赋值输出。`&`符号表示逻辑与运算。