要求对上述电路编写可综合的verilog代码,编写testbench
时间: 2024-05-19 09:10:58 浏览: 15
module ALU(
input [7:0] A,
input [7:0] B,
input [2:0] opcode,
output reg [7:0] out
);
always @ (*) begin
case(opcode)
3'b000: out = A + B;
3'b001: out = A - B;
3'b010: out = A & B;
3'b011: out = A | B;
3'b100: out = A ^ B;
3'b101: out = ~(A & B);
3'b110: out = ~(A | B);
3'b111: out = ~(A ^ B);
endcase
end
endmodule
module testbench;
reg [7:0] A;
reg [7:0] B;
reg [2:0] opcode;
wire [7:0] out;
ALU UUT(
.A(A),
.B(B),
.opcode(opcode),
.out(out)
);
initial begin
A = 8'h0A;
B = 8'h05;
opcode = 3'b000;
#10;
A = 8'h0F;
B = 8'h06;
opcode = 3'b001;
#10;
A = 8'hF0;
B = 8'h0F;
opcode = 3'b010;
#10;
A = 8'hA5;
B = 8'h5A;
opcode = 3'b011;
#10;
A = 8'hAA;
B = 8'h55;
opcode = 3'b100;
#10;
A = 8'hF0;
B = 8'h0F;
opcode = 3'b101;
#10;
A = 8'hA5;
B = 8'h5A;
opcode = 3'b110;
#10;
A = 8'hAA;
B = 8'h55;
opcode = 3'b111;
#10;
$finish;
end
endmodule
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