用verilog对电路按模块化进行拆分，完成子模块的设计完成1秒定时器及testbench文件编写，完成60进制计数器电路及及testbench文件编写，每隔1秒数码管从00-59显示的testbench文件编写

以下是Verilog代码：

1秒定时器模块：

module timer_1s (
    input clk,
    input reset,
    output reg out
);

reg [23:0] count;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 0;
        out <= 0;
    end else begin
        count <= count + 1;
        if (count == 24000000) begin // 1s
            out <= ~out;
            count <= 0;
        end
    end
end

endmodule

1秒定时器测试模块：

module timer_1s_tb;

reg clk;
reg reset;
wire out;

timer_1s timer_1s_inst (
    .clk(clk),
    .reset(reset),
    .out(out)
);

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

endmodule

60进制计数器模块：

module counter_60 (
    input clk,
    input reset,
    output [5:0] hex0,
    output [5:0] hex1
);

reg [5:0] count;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 0;
    end else begin
        if (count == 59) begin
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end
end

assign hex0 = count % 10;
assign hex1 = count / 10;

endmodule

60进制计数器测试模块：

module counter_60_tb;

reg clk;
reg reset;
wire [5:0] hex0;
wire [5:0] hex1;

counter_60 counter_60_inst (
    .clk(clk),
    .reset(reset),
    .hex0(hex0),
    .hex1(hex1)
);

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

endmodule

1秒定时器和60进制计数器的组合模块：

module timer_counter (
    input clk,
    input reset,
    output [6:0] hex0,
    output [6:0] hex1
);

wire timer_out;
counter_60 counter_60_inst (
    .clk(clk),
    .reset(reset),
    .hex0(hex0),
    .hex1(hex1)
);
timer_1s timer_1s_inst (
    .clk(clk),
    .reset(reset),
    .out(timer_out)
);

assign {hex1, hex0} = {hex1, hex0} + timer_out;

endmodule

1秒定时器和60进制计数器的组合测试模块：

module timer_counter_tb;

reg clk;
reg reset;
wire [6:0] hex0;
wire [6:0] hex1;

timer_counter timer_counter_inst (
    .clk(clk),
    .reset(reset),
    .hex0(hex0),
    .hex1(hex1)
);

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

initial begin
    reset = 1;
    #10 reset = 0;
end

endmodule