fpga的数字时钟vhdl代码

下面是一个简单的FPGA数字时钟的VHDL代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity digital_clock is
    Port ( clock_in : in  STD_LOGIC;
           reset_in : in  STD_LOGIC;
           enable_in : in  STD_LOGIC;
           clk_out : out  STD_LOGIC_VECTOR (3 downto 0);
           min_out : out  STD_LOGIC_VECTOR (5 downto 0);
           sec_out : out  STD_LOGIC_VECTOR (5 downto 0));
end digital_clock;

architecture Behavioral of digital_clock is

    signal clk_counter : unsigned(15 downto 0) := (others => '0');
    signal sec_counter : unsigned(5 downto 0) := (others => '0');
    signal min_counter : unsigned(5 downto 0) := (others => '0');

begin

    process(clock_in, reset_in, enable_in)
    begin
        if reset_in = '1' then
            clk_counter <= (others => '0');
            sec_counter <= (others => '0');
            min_counter <= (others => '0');
            clk_out <= (others => '0');
            sec_out <= (others => '0');
            min_out <= (others => '0');
        elsif rising_edge(clock_in) then
            if enable_in = '1' then
                -- Clock Counter
                clk_counter <= clk_counter + 1;
                if clk_counter = 50000 then
                    clk_counter <= (others => '0');
                    -- Seconds Counter
                    sec_counter <= sec_counter + 1;
                    if sec_counter = 60 then
                        sec_counter <= (others => '0');
                        -- Minutes Counter
                        min_counter <= min_counter + 1;
                        if min_counter = 60 then
                            min_counter <= (others => '0');
                        end if;
                    end if;
                end if;
            end if;
        end if;

        clk_out <= std_logic_vector(to_unsigned(clk_counter(3 downto 0), 4));
        sec_out <= std_logic_vector(to_unsigned(sec_counter, 6));
        min_out <= std_logic_vector(to_unsigned(min_counter, 6));

    end process;

end Behavioral;

这个代码使用了一个时钟计数器来计数时钟周期，并且在特定的时钟周期，对秒和分钟计数器进行更新。最后，这个代码将计数器的值转换为二进制数，并将其赋给输出端口。