三元组可以这么写吗 h_valid = ( 10'd20 <= cnt_h <= 10'd419) ? 1'b1 : 1'b0
时间: 2024-02-15 12:03:36 浏览: 32
不可以,因为在 Verilog 中,不能像 Python 一样使用类似于 `(a <= b <= c)` 的形式来表示范围。正确的写法应该是:
```
h_valid = (cnt_h >= 10'd20) && (cnt_h <= 10'd419) ? 1'b1 : 1'b0;
```
或者:
```
h_valid = ((cnt_h >= 10'd20) && (cnt_h <= 10'd419)) ? 1'b1 : 1'b0;
```
这里使用了逻辑运算符 `&&` 来表示“与”的关系。
相关问题
assign led2=(key2_r2&&(cnt==8'd20))?0:key2_r2?1:0;
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assign led2=(key2_r2&&(cnt==8'd20))?0:key2_r2?1:0;是什么意思
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