编写一个能够并行处理1024bit数据的crc校验码生成模块，使用verilog

module crc_generator(
input clk,
input reset,
input [1023:0] data_in,
output reg [31:0] crc_out
);

reg [1023:0] shift_reg;
reg [31:0] crc_reg;
reg [31:0] poly = 32'h04C11DB7; // CRC-32 polynomial

always @(posedge clk) begin
if (reset) begin // Reset shift register and CRC register
shift_reg <= 0;
crc_reg <= 0;
end else begin
shift_reg <= {shift_reg[1022:0], data_in}; // Shift in new data
for (int i = 1023; i >= 0; i--) begin
if (shift_reg[i]) begin // If MSB of shift register is set
shift_reg[i:0] = shift_reg[i:0] ^ (poly << (i-31)); // XOR with polynomial shifted to MSB position
end
end
crc_reg <= shift_reg[31:0]; // CRC is the last 32 bits of the shift register
end
end

assign crc_out = crc_reg;

endmodule