Verilog74161六进制计数器模块

以下是 Verilog 代码实现一个六进制计数器模块：

module hex_counter(
    input clk, // 时钟信号
    input rst, // 复位信号
    output reg [5:0] count // 输出计数值，六位二进制数
);

always @(posedge clk or posedge rst) begin
    if (rst) begin
        count <= 6'h0; // 复位计数器
    end else begin
        case(count)
            6'h0: count <= 6'h1;
            6'h1: count <= 6'h2;
            6'h2: count <= 6'h3;
            6'h3: count <= 6'h4;
            6'h4: count <= 6'h5;
            6'h5: count <= 6'h6;
            6'h6: count <= 6'h7;
            6'h7: count <= 6'h8;
            6'h8: count <= 6'h9;
            6'h9: count <= 6'ha;
            6'ha: count <= 6'hb;
            6'hb: count <= 6'hc;
            6'hc: count <= 6'hd;
            6'hd: count <= 6'he;
            6'he: count <= 6'hf;
            6'hf: count <= 6'h10;
            6'h10: count <= 6'h11;
            6'h11: count <= 6'h12;
            6'h12: count <= 6'h13;
            6'h13: count <= 6'h14;
            6'h14: count <= 6'h15;
            6'h15: count <= 6'h16;
            6'h16: count <= 6'h17;
            6'h17: count <= 6'h18;
            6'h18: count <= 6'h19;
            6'h19: count <= 6'h1a;
            6'h1a: count <= 6'h1b;
            6'h1b: count <= 6'h1c;
            6'h1c: count <= 6'h1d;
            6'h1d: count <= 6'h1e;
            6'h1e: count <= 6'h1f;
            6'h1f: count <= 6'h0;
            default: count <= 6'h0; // 防止出错
        endcase
    end
end

endmodule

该模块包含一个时钟信号和一个复位信号作为输入，以及一个六位二进制计数值作为输出。每当时钟信号上升沿到来时，计数器将递增一次。当复位信号为高电平时，计数器将被重置为零。计数器的计数范围为 0-31，对应六进制数 0-1f。