用SV书写7位数据位，1位偶校验，115200bps的uart串行发送端 2.用SV书写对应的行为模型（接收端），并输出激励中的字节值，奇偶性错误的，输出校验错误3.编写testcase

1. 用SV书写7位数据位，1位偶校验，115200bps的uart串行发送端

module uart_tx
  #(parameter BAUD_RATE = 115200)
  (
    input clk,
    input rst_n,
    input logic [6:0] data,
    output logic tx
  );
  
  logic [9:0] counter;
  logic [7:0] data_parity;
  logic parity;
  logic start_bit;
  logic stop_bit;

  assign data_parity = {data, parity};
  
  always_ff @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
      counter <= 10'b0;
      tx <= 1'b1;
      parity <= 1'b1;
      start_bit <= 1'b0;
      stop_bit <= 1'b0;
    end else begin
      case (counter)
        10'b0000000000: begin
          start_bit <= 1'b0;
          stop_bit <= 1'b0;
          counter <= 10'b0000000001;
          tx <= 1'b0;
        end
        10'b0000000001: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000010;
          parity <= ^data;
        end
        10'b0000000010: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000011;
          tx <= data_parity[0];
        end
        10'b0000000011: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000100;
          tx <= data_parity[1];
        end
        10'b0000000100: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000101;
          tx <= data_parity[2];
        end
        10'b0000000101: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000110;
          tx <= data_parity[3];
        end
        10'b0000000110: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000000111;
          tx <= data_parity[4];
        end
        10'b0000000111: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000001000;
          tx <= data_parity[5];
        end
        10'b0000001000: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000001001;
          tx <= data_parity[6];
        end
        10'b0000001001: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b0;
          counter <= 10'b0000001010;
          tx <= 1'b1;
        end
        10'b0000001010: begin
          start_bit <= 1'b1;
          stop_bit <= 1'b1;
          counter <= 10'b0000000000;
          tx <= 1'b1;
        end
      endcase
    end
  end
endmodule

2. 用SV书写对应的行为模型（接收端），并输出激励中的字节值，奇偶性错误的，输出校验错误

module uart_rx
  #(parameter BAUD_RATE = 115200)
  (
    input clk,
    input rst_n,
    input rx,
    output logic [6:0] data,
    output logic parity_error
  );
  
  logic [9:0] counter;
  logic [7:0] rx_buffer;
  logic data_valid;
  logic parity;
  logic start_bit;
  logic stop_bit;

  assign data = rx_buffer[6:0];
  
  always_ff @(posedge clk, negedge rst_n) begin
    if (!rst_n) begin
      counter <= 10'b0;
      rx_buffer <= 8'b0;
      parity <= 1'b1;
      data_valid <= 1'b0;
      start_bit <= 1'b0;
      stop_bit <= 1'b0;
      parity_error <= 1'b0;
    end else begin
      case (counter)
        10'b0000000000: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000001;
        end
        10'b0000000001: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000010;
        end
        10'b0000000010: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000011;
        end
        10'b0000000011: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000100;
        end
        10'b0000000100: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000101;
        end
        10'b0000000101: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000110;
        end
        10'b0000000110: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000000111;
        end
        10'b0000000111: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000001000;
        end
        10'b0000001000: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000001001;
          parity <= rx;
        end
        10'b0000001001: begin
          start_bit <= rx;
          stop_bit <= 1'b0;
          counter <= 10'b0000001010;
          rx_buffer <= {rx_buffer[6:0], rx};
        end
        10'b0000001010: begin
          start_bit <= rx;
          stop_bit <= rx;
          counter <= 10'b0000000000;
          data_valid <= 1'b1;
        end
      endcase
    end
  end
  
  always_comb begin
    if (data_valid) begin
      if (parity !== ^rx_buffer) begin
        parity_error <= 1'b1;
      end
    end
  end
endmodule

3. 编写testcase

module uart_tb;
  logic clk;
  logic rst_n;
  logic tx;
  logic rx;
  logic [6:0] data;
  logic parity_error;

  uart_tx #(
    .BAUD_RATE(115200)
  ) dut_tx (
    .clk(clk),
    .rst_n(rst_n),
    .data(data),
    .tx(tx)
  );
  
  uart_rx #(
    .BAUD_RATE(115200)
  ) dut_rx (
    .clk(clk),
    .rst_n(rst_n),
    .rx(rx),
    .data(data),
    .parity_error(parity_error)
  );
  
  initial begin
    clk = 1'b0;
    forever #5 clk = ~clk;
  end
  
  initial begin
    rst_n = 1'b0;
    #10;
    rst_n = 1'b1;
  end
  
  initial begin
    $monitor("time=%0d tx=%b rx=%b data=%0d parity_error=%b", $time, tx, rx, data, parity_error);
    
    // test case 1: send "hello, world!"
    data = 'h;
    #1000;
    data = 'e;
    #1000;
    data = 'l;
    #1000;
    data = 'l;
    #1000;
    data = 'o;
    #1000;
    data = ',;
    #1000;
    data = ' ';
    #1000;
    data = 'w;
    #1000;
    data = 'o;
    #1000;
    data = 'r;
    #1000;
    data = 'l;
    #1000;
    data = 'd;
    #1000;
    
    // test case 2: send odd parity data
    data = 7'b0001100;
    #1000;
    
    // test case 3: send even parity data
    data = 7'b0001101;
    #1000;
  end
endmodule