LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY tong IS PORT( Vin : IN STD_LOGIC_VECTOR(7 DOWNTO 0); shift : IN STD_LOGIC_VECTOR(2 downto 0); Vo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END tong; ARCHITECTURE behavior OF tong IS BEGIN process(shift,Vin) VARIABLE temp1:STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE temp2:STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE temp3:STD_LOGIC_VECTOR(7 DOWNTO 0); begin -- 第一级移位操作 IF(shift(0)='0') THEN temp1 := Vin; ELSE temp1(0):='0'; for i IN 1 to Vin'HIGH LOOP temp1(i):=Vin(i-1); END LOOP; END IF; -- 第二级移位操作 IF(shift(1)='0') THEN temp2:=temp1; ELSE temp2(0 to 1):="00"; -- 清零前两位 for i IN 2 to Vin'HIGH LOOP temp2(i):=temp1(i-2); END LOOP; END IF; -- 第三级移位操作 IF(shift(2)='0') THEN temp3:=temp2; ELSE temp3(0 to 2):="000"; -- 清零前三位 for i IN 3 to Vin'HIGH LOOP temp3(i):=temp2(i-3); END LOOP; END IF; Vo<=temp3; -- 输出结果 end process; END behavior;将这个代码改成右移的桶式移位寄存器VHDL版
时间: 2023-12-06 21:42:47 浏览: 61
PID.rar_PID控制IEEE文章_VHDL PID_logic_pid vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY tong IS
PORT(
Vin : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
shift : IN STD_LOGIC_VECTOR(2 downto 0);
Vo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END tong;
ARCHITECTURE behavior OF tong IS
BEGIN
process(shift,Vin)
VARIABLE temp1:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE temp2:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE temp3:STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
-- 第一级移位操作
IF(shift(0)='0') THEN
temp1 := Vin;
ELSE
temp1(7):='0';
for i IN 0 to Vin'HIGH-1 LOOP
temp1(i):=Vin(i+1);
END LOOP;
END IF;
-- 第二级移位操作
IF(shift(1)='0') THEN
temp2:=temp1;
ELSE
temp2(7 downto 1):=temp1(6 downto 0);
temp2(0):='0';
END IF;
-- 第三级移位操作
IF(shift(2)='0') THEN
temp3:=temp2;
ELSE
temp3(7 downto 2):=temp2(5 downto 0);
temp3(0 to 1):="00";
END IF;
Vo<=temp3; -- 输出结果
end process;
END behavior;
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