// 显示输入的密码 if (delete_count == 2'b00 && password_count > 0) begin // 将输入的密码存储到display寄存器中 display <= {input_password,4'b0000}[(count4)+3:(count4)]; count <= count + 2'b01;last_password_count <= password_count; end else if (delete_count == 2'b01 && last_password_count > 0) begin // 删除输入的密码 display <= display-4'b0001; count <= count - 2'b01; last_password_count <= last_password_count - 1; end;// Error (10170): Verilog HDL syntax error at keshe9.v(60) near text "["; expecting ";"还是这个错误改了之后的代码是什么
时间: 2023-07-16 18:13:08 浏览: 63
你需要在 `display` 寄存器的赋值语句中加入一个分号,代码如下所示:
```
// 显示输入的密码
if (delete_count == 2'b00 && password_count > 0) begin
// 将输入的密码存储到display寄存器中
display <= {input_password,4'b0000}[(count4)+3:(count4)];
count <= count + 2'b01;
last_password_count <= password_count;
end else if (delete_count == 2'b01 && last_password_count > 0) begin
// 删除输入的密码
display <= display-4'b0001;
count <= count - 2'b01;
last_password_count <= last_password_count - 1;
end; // 加入分号
```
这样就可以解决 Verilog HDL syntax error at keshe9.v(60) near text "["; expecting ";" 的问题了。
相关问题
// 显示输入的密码if (delete_count == 2'b00 && password_count > 0) begin // 将输入的密码存储到display寄存器中 display <= {input_password,4'b0000}[(count4)+3:(count4)]; count <= count + 2'b01; last_password_count <= password_count;end else if (delete_count == 2'b01 && last_password_count > 0) begin // 删除输入的密码 display <= display-4'b0001; count <= count - 2'b01; last_password_count <= last_password_count - 1;end; // 加入分号 Error (10170): Verilog HDL syntax error at keshe9.v(60) near text "["; expecting ";"这个错误改完之后的代码
如果你想在Verilog中使用花括号来创建一个选择器,你需要在使用选择器前加上一个反斜杠,如下所示:
```
// 显示输入的密码
if (delete_count == 2'b00 && password_count > 0) begin
// 将输入的密码存储到display寄存器中
display <= {input_password,4'b0000}[((count4)+3):(count4)];
count <= count + 2'b01;
last_password_count <= password_count;
end else if (delete_count == 2'b01 && last_password_count > 0) begin
// 删除输入的密码
display <= display-4'b0001;
count <= count - 2'b01;
last_password_count <= last_password_count - 1;
end;
```
这样,Verilog就会将花括号视为选择器,而不是一个新的语法结构。
改写一下这段代码,使得寄存器地址支持16bit读写,现在这段是只支持8bit读写://FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[7:1])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase
以下是修改后的代码,支持16bit读写:
//FSM always @ (posedge clk or negedge rst) if (~rst) i2c_state<=3'b000;//idle else i2c_state<= next_i2c_state; //////////Modified on 25 november.write Address is 30H; Read Address is 31H///// always @(i2c_state or stopf or startf or cnt or sft or sadr or hf or scl_neg or cnt) case(i2c_state) 3'b000: //This state is the initial state,idle state begin if (startf)next_i2c_state<= 3 b001;//start else next_i2c_state <= i2c_state; end 3b001://This state is the device address detect & trigger begin if(stopf)next_i2c_state<=3'b000; else begin if((cnt==4'h9)&&({sft[0],hf} ==2'b00) && (scl_neg ==1'b1)&&(sadr ==sft[15:2])) next i2c_ state<=3'b010;//write: i2c adderss is 00110000 and ACK is sampled //so {sft[0],hf} is 2'b00 else if ((cnt==4'h9)&&({sft[0],hf} ==2'b10) && (scl_neg ==1'b1)&&(sadr ==sft[15:2])) next i2c_ state<=3'b011;//read:i2c adderss is 00110001 and ACK is sampled //so {sft[0],hf} is 2'b10 else if((cnt ==4'h9) && (scl_neg == 1'b1)) next_ i2c_state<=3 'b000;//when the address accepted does not match the SADR, //the state comes back else next_i2c_state<=i2c_state; end end 3'b010: //This state is the register address detect &&trigger begin if (stopf)next_i2c_state<=3'b000; else if (startf)next_i2c_state<=3'b001; else if ((cnt ==4'h9) && (scl_neg == 1'b1)) next_i2c _state<=3'b10 else next i2c_state<=i2c_state; end 3'b011: //This state is the register data read begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3'b001; else next_12c_state<=i2c_state; end 3'b100: //This state is the register data write begin if (stopf)next_i2c _state<=3'b000; else if (startf) next_i2c _state<=3b001; else next_i2c_state<=i2c_state; end default://safe mode control next_i2c_state <= 3'b000; endcase
修改的内容:
1. 在设备地址检测&触发状态中,将设备地址的位数扩展到16位,即将sft[7:1]修改为sft[15:2]。
2. 在写寄存器地址检测&触发状态中,同样将地址的位数扩展到16位。
3. 在读寄存器数据状态和写寄存器数据状态中,没有需要修改的地方。
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