用vhdl写一个四位全加器

以下是一个四位全加器的VHDL代码：

-- 4-Bit Full Adder
library ieee;
use ieee.std_logic_1164.all;

entity four_bit_adder is
    port(
        a: in std_logic_vector(3 downto 0);
        b: in std_logic_vector(3 downto 0);
        cin: in std_logic;
        sum: out std_logic_vector(3 downto 0);
        cout: out std_logic
    );
end four_bit_adder;

architecture behavioral of four_bit_adder is
begin
    -- First Full Adder
    full_adder1: entity work.full_adder port map(
        a => a(0),
        b => b(0),
        cin => cin,
        sum => sum(0),
        cout => cout1
    );

    -- Second Full Adder
    full_adder2: entity work.full_adder port map(
        a => a(1),
        b => b(1),
        cin => cout1,
        sum => sum(1),
        cout => cout2
    );

    -- Third Full Adder
    full_adder3: entity work.full_adder port map(
        a => a(2),
        b => b(2),
        cin => cout2,
        sum => sum(2),
        cout => cout3
    );

    -- Fourth Full Adder
    full_adder4: entity work.full_adder port map(
        a => a(3),
        b => b(3),
        cin => cout3,
        sum => sum(3),
        cout => cout
    );
end behavioral;

这个代码使用了四个一位全加器来实现一个四位全加器。每个一位全加器都是使用一个名为`full_adder`的实体来实现的。每个实体都有输入`a`和`b`，表示要相加的两个位，一个输入`cin`，表示上一个位的进位，一个输出`sum`，表示相加的结果，一个输出`cout`，表示下一个位的进位。在这个代码中，我们使用了四个一位全加器，分别用来计算四个位的和，并将所有的进位相加得到最终的进位。