设计一段verilog及其testbench，要求将16个10位大小的向量分别与6个10位大小的向量相乘，结果选取向量相乘结果中最大值对应的16个10位大小的向量输出，

以下是Verilog代码：

module vector_multiplication (
    input [15:0] vec[0:15],
    input [5:0] coef[0:5],
    output reg [15:0] max_vec
);

reg [15:0] result[0:15];
reg [15:0] max_result;

integer i, j;

always @(*) begin
    for (i = 0; i < 16; i = i + 1) begin
        result[i] = vec[i] * coef[0];
        for (j = 1; j < 6; j = j + 1) begin
            result[i] = result[i] + vec[i] * coef[j];
        end
    end
    
    max_result = result[0];
    max_vec = vec[0];
    for (i = 1; i < 16; i = i + 1) begin
        if (result[i] > max_result) begin
            max_result = result[i];
            max_vec = vec[i];
        end
    end
end

endmodule

以下是对应的testbench代码：

module testbench;

reg [15:0] vec[0:15];
reg [5:0] coef[0:5];
wire [15:0] max_vec;

integer i;

vector_multiplication dut (
    .vec(vec),
    .coef(coef),
    .max_vec(max_vec)
);

initial begin
    // Initialize input vectors and coefficients
    for (i = 0; i < 16; i = i + 1) begin
        vec[i] = $random;
    end
    for (i = 0; i < 6; i = i + 1) begin
        coef[i] = $random;
    end
    
    // Apply input vectors and coefficients to DUT
    #1;
    for (i = 0; i < 16; i = i + 1) begin
        $display("vec[%0d] = %d", i, vec[i]);
    end
    for (i = 0; i < 6; i = i + 1) begin
        $display("coef[%0d] = %d", i, coef[i]);
    end
    #1;
    
    // Check output max_vec
    $display("max_vec = %d", max_vec);
    
    // End simulation
    #1;
    $finish;
end

endmodule