请为我写一段verilog的UART发送端代码

module uart_tx(
input clk,
input rstn,
input [7:0] data_in,
input start_tx,
output reg tx_busy,
output reg tx_done,
output reg [3:0] tx_state,
output reg tx_out
);

parameter IDLE = 2'b00;
parameter START_BIT = 2'b01;
parameter DATA_BIT = 2'b10;
parameter STOP_BIT = 2'b11;

reg [3:0] next_state;
reg [3:0] current_state;
reg [3:0] count;
reg [3:0] bit_count;
reg [3:0] stop_count;
reg [7:0] data_out;

assign tx_out = ~data_out[0]; // Inverted data_out[0] for start bit

always @(posedge clk or negedge rstn) begin
if (~rstn) begin
tx_busy <= 1'b0;
tx_done <= 1'b0;
tx_state <= IDLE;
data_out <= 8'h00;
count <= 4'd0;
bit_count <= 4'd0;
stop_count <= 4'd0;
current_state <= IDLE;
next_state <= IDLE;
end
else begin
current_state <= next_state;

case(current_state)
IDLE: begin
if (start_tx) begin
tx_busy <= 1'b1;
tx_done <= 1'b0;
next_state <= START_BIT;
count <= 4'd0;
bit_count <= 4'd0;
stop_count <= 4'd0;
data_out <= {1'b0, data_in, 1'b1}; // Add start and stop bit
end
else begin
tx_busy <= 1'b0;
tx_done <= 1'b0;
next_state <= IDLE;
end
end

START_BIT: begin
if (count < 4'd16) begin // 16 cycles for 115200 baudrate
count <= count + 1;
next_state <= START_BIT;
end
else begin
count <= 4'd0;
next_state <= DATA_BIT;
end
end

DATA_BIT: begin
if (bit_count < 4'd8) begin
data_out <= {data_out[6:0], data_out[7]};
bit_count <= bit_count + 1;
next_state <= DATA_BIT;
end
else begin
bit_count <= 4'd0;
next_state <= STOP_BIT;
end
end

STOP_BIT: begin
if (stop_count < 4'd16) begin // 16 cycles for 115200 baudrate
stop_count <= stop_count + 1;
next_state <= STOP_BIT;
end
else begin
stop_count <= 4'd0;
next_state <= IDLE;
tx_done <= 1'b1;
tx_busy <= 1'b0;
end
end
endcase
end
end

endmodule