纠正以下verilog语句： module controller(func,op,RegDst,RegWrite,ALUSrc,MemWrite,MemRead,MemtoReg,Branch,ALU_op ); input [5:0] op,func; output RegDst,RegWrite,ALUSrc,MemWrite,MemRead,MemtoReg,Branch; output [2:0] ALU_op; wire [1:0] ALUctr; reg RegDst,RegWrite,ALUSrc,MemWrite,MemRead,MemtoReg,Branch; reg [2:0] ALU_op; always @(posedge clk) begin case (op) 6'b000000: assign RegDst = 1&RegWrite = 1&ALUSrc = 0&MemWrite = 0&MemRead = 0&MemtoReg = 0&Branch = 0&AlUctr = 10; 6'b100011: assign RegDst = 0&RegWrite = 1&ALUSrc = 1&MemWrite = 0&MemRead = 1&MemtoReg = 1&Branch = 0&AlUctr = 00; 6'b101011: assign RegDst = 1&RegWrite = 0&ALUSrc = 1&MemWrite = 1&MemRead = 0&MemtoReg = 0&Branch = 0&AlUctr = 00; 6'b000100: assign RegDst = 1&RegWrite = 0&ALUSrc = 0&MemWrite = 0&MemRead = 0&MemtoReg = 0&Branch = 1&AlUctr = 01; 6'b001111: assign RegDst = 0&RegWrite = 1&ALUSrc = 1&MemWrite = 0&MemRead = 0&MemtoReg = 0&Branch = 0&AlUctr = 11; default : assign RegDst = 'bx&RegWrite = 'bx&ALUSrc = 'bx&MemWrite = 'bx&MemRead = 'bx&MemtoReg = 'bx&Branch = 'bx&AlUctr = 'bx; endcase end begin if (ALUctr == 10) case(func) 6'b100000: assign ALU_Op = 3'b000; 6'b100010: assign ALU_Op = 3'b100; 6'b100100: assign ALU_Op = 3'b001; 6'b100101: assign ALU_Op = 3'b101; 6'b100110: assign ALU_Op = 3'b010; default:assign ALU_Op='bx; endcase else if (ALUctr == 00) assign ALU_op = 3'b000; else if (ALUctr == 01) assign ALU_op = 3'b100; else if (ALUctr==11) assign ALU_op = 3'b110; end endmodule

module controller (
input [5:0] func, op,
output RegDst, RegWrite, ALUSrc, MemWrite, MemRead, MemtoReg, Branch,
output [2:0] ALU_op
);

wire [1:0] ALUctr;
reg RegDst, RegWrite, ALUSrc, MemWrite, MemRead, MemtoReg, Branch;
reg [2:0] ALU_op;

always @(posedge clk) begin
case (op)
6'b000000: begin
RegDst = 1;
RegWrite = 1;
ALUSrc = 0;
MemWrite = 0;
MemRead = 0;
MemtoReg = 0;
Branch = 0;
ALUctr = 2'b10;
end
6'b100011: begin
RegDst = 0;
RegWrite = 1;
ALUSrc = 1;
MemWrite = 0;
MemRead = 1;
MemtoReg = 1;
Branch = 0;
ALUctr = 2'b00;
end
6'b101011: begin
RegDst = 1;
RegWrite = 0;
ALUSrc = 1;
MemWrite = 1;
MemRead = 0;
MemtoReg = 0;
Branch = 0;
ALUctr = 2'b00;
end
6'b000100: begin
RegDst = 1;
RegWrite = 0;
ALUSrc = 0;
MemWrite = 0;
MemRead = 0;
MemtoReg = 0;
Branch = 1;
ALUctr = 2'b01;
end
6'b001111: begin
RegDst = 0;
RegWrite = 1;
ALUSrc = 1;
MemWrite = 0;
MemRead = 0;
MemtoReg = 0;
Branch = 0;
ALUctr = 2'b11;
end
default: begin
RegDst = 'bx;
RegWrite = 'bx;
ALUSrc = 'bx;
MemWrite = 'bx;
MemRead = 'bx;
MemtoReg = 'bx;
Branch = 'bx;
ALUctr = 'bx;
end
endcase
end

always @(*) begin
case (ALUctr)
2'b10: begin
case (func)
6'b100000: ALU_op = 3'b000;
6'b100010: ALU_op = 3'b100;
6'b100100: ALU_op = 3'b001;
6'b100101: ALU_op = 3'b101;
6'b100110: ALU_op = 3'b010;
default: ALU_op = 'bx;
endcase
end
2'b00: ALU_op = 3'b000;
2'b01: ALU_op = 3'b100;
2'b11: ALU_op = 3'b110;
default: ALU_op = 'bx;
endcase
end

endmodule