Fpga基于两位数码管计数器设计出简单的频率计，可测频率范围为1-99HZ，请给出设计思路，原理及代码

设计思路：

对于基于FPGA的频率计，我们可以设计一个计数器，通过计数器的计数值和计时器的时间间隔计算得到输入信号的频率。具体设计可以采用FPGA自带的计数器模块，通过两个七段数码管显示计数值，同时采用时钟模块对计时器进行控制，最终计算出频率值并在数码管上显示。

原理：

基于FPGA的频率计主要原理是通过计数器计算输入信号的周期，得到信号的频率。FPGA上的计数器模块可以实现计数器的功能，通过计时器模块控制计数周期，计算出输入信号的频率。同时使用两个七段数码管将计数值显示出来，方便用户观察。

代码：

以下是基于VHDL语言的FPGA频率计设计代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity freq_counter is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           in_signal : in  STD_LOGIC;
           seg_out : out  STD_LOGIC_VECTOR (6 downto 0);
           dig_out : out  STD_LOGIC_VECTOR (1 downto 0));
end freq_counter;

architecture Behavioral of freq_counter is

    signal clk_cnt : unsigned(27 downto 0);
    signal cnt : unsigned(9 downto 0);
    signal freq : unsigned(9 downto 0);
    signal seg_data : std_logic_vector(6 downto 0);
    signal dig_data : std_logic_vector(1 downto 0);
    signal clk_en : std_logic;
    signal clk_sec : std_logic;

begin

    clk_en <= clk_sec AND in_signal;

    process(reset, clk_en, clk)
    begin
        if reset = '1' then
            clk_cnt <= (others => '0');
            cnt <= (others => '0');
            freq <= (others => '0');
            seg_data <= "0000001";
            dig_data <= "00";
        elsif rising_edge(clk) then
            clk_cnt <= clk_cnt + 1;
            if clk_cnt = "10111110101111000010111000" then
                cnt <= cnt + 1;
                clk_cnt <= (others => '0');
            end if;
        end if;
    end process;

    freq <= cnt * 10;

    process(freq)
    begin
        case freq is
            when 0 to 9 => seg_data <= "0011111";
            when 10 to 19 => seg_data <= "0000110";
            when 20 to 29 => seg_data <= "0101101";
            when 30 to 39 => seg_data <= "0100111";
            when 40 to 49 => seg_data <= "0110010";
            when 50 to 59 => seg_data <= "0110111";
            when 60 to 69 => seg_data <= "0111111";
            when 70 to 79 => seg_data <= "0000111";
            when 80 to 89 => seg_data <= "0111111";
            when 90 to 99 => seg_data <= "0110111";
            when others => seg_data <= "1111111";
        end case;
    end process;

    process(cnt)
    begin
        case cnt is
            when 0 to 9 => dig_data <= "00";
            when 10 to 99 => dig_data <= "01";
            when others => dig_data <= "11";
        end case;
    end process;

    seg_out <= seg_data;
    dig_out <= dig_data;

end Behavioral;

该代码实现了一个简单的频率计，通过计时器和计数器实现对输入信号的计数，最终计算出信号的频率值并在两个七段数码管上进行显示。