NVIDIA Xavier SOC技术参考手册：系统架构与控制细节

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NVIDIA Xavier Series System-on-Chip (SoC) 是一款专为高性能人工智能 (AI) 和计算机视觉应用设计的嵌入式处理器。这份Technical Reference Manual (TRM) v1.4p提供了对Xavier系列SoC内部逻辑组织和控制的深入解析。它主要关注那些与外部设备交互的模块，或者是控制芯片基本操作的核心组件。文档详尽地阐述了这些模块的功能概述、编程指导和相应的寄存器列表，以便于开发者理解和利用。手册的目的是帮助工程师了解如何有效地与Xavier的各个模块进行交互，包括但不限于处理外部接口（如USB、PCIe等）、管理硬件加速单元（如视频和图形处理器）以及进行底层系统控制。然而，需要注意的是，由于这些硬件加速单元是由NVIDIA提供的软件驱动管理，因此它们的具体实现细节并未在TRM中详细记录。 TRM包含了以下内容： 1. **Revision History**：这部分列出了文档的不同版本更新，方便读者追踪和理解技术变化。 2. **Introduction**： - **Reading Register Tables**：指南介绍如何阅读和解读SoC中的寄存器，这对于硬件开发者调试和配置硬件至关重要。 - **Units**：这部分可能涉及系统的架构单元划分，例如CPU核心、GPU、神经网络加速器(Neural Processing Unit, NPU)等，以及它们之间的协作方式。 - **Glossary**：提供了一个专业术语表，解释了文中使用的特定技术词汇，便于非专家理解。 3. **Module Descriptions and Programming Guidelines**：详细介绍了各个功能模块的描述、功能特性、接口规范和编程接口，包括中断管理、时钟管理、电源管理等。 4. **Register Listings**：提供了SoC内部寄存器的详细列表，包括地址、位宽、功能和用途，这对于驱动程序开发者编写和调试代码非常有用。 NVIDIA Xavier TRM v1.4p是设计者和开发者必备的参考资料，它不仅描绘了Xavier SoC的整体架构，还提供了实现高效集成和优化应用所需的底层信息。通过阅读和理解这份手册，用户可以更好地利用Xavier的性能优势，并确保他们的设计与NVIDIA的优化策略保持一致。

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NVIDIA Xavier Series System-on-Chip

Technical Reference Manual

Parity Protection: per register Parity diagnostic in hardware implemented by safety critical IPs. The Parity Diagnostic

detects random faults in the register fields.

‘Y’ indicates the field is continuously checked by the Parity Diagnostic of the register. Single bit flips in the register,

when not intended, is reported as a fault.

‘N’ indicates the field is not checked by the Parity Diagnostic of the register.

If all fields of the register have Parity Protection Column as 'N', the register does not implement any hardware based

Parity Diagnostic.

Reset: gives the power-on reset value in 32-bit binary. A value of x implies that the register bit has an undefined

value at reset. A hexadecimal value is listed for convenience, where appropriate.

Default: only displayed if the default setting is different from the Reset value.

Unspecified bits may not appear in tables (see example below). Unspecified bits should be written with their

Reset values, while reads return an unknown value.

NVIDIA Xavier Series System-on-Chip

Technical Reference Manual

Among other things, this convention uses an 'i' to indicate the binary convention, and its absence to indicate

decimal. So, 1 KiB is 2 or 1,024 bytes, and 1 KB is 10 or 1,000 bytes. Similarly it uses:

10 3

Mi for 2 and M for 10

20 6

Gi for 2 and G for 10

30 9

Ti for 2 and T for 10

40 12

2.3 Glossary

This glossary is intended to cover the acronyms used in this document; along with some others related to the

ARM SoC world. Many other acronyms in this document are in broad engineering use and are not documented

here.

Term Definition

32K or 32k 32,768 Hz oscillator clock. Any references to 32k, 32 kHz, 32 KHz or 32K in the context of this clock should

always be interpreted as referring to a frequency of 32,768 Hz.

444/422/420 Pixel storage formats, 444 refers to formats where there are equal amounts of information for all three elements,

422 and 420 refer to formats where the color difference information is stored at half-resolution in either one

direction or both.

ADAS Advanced Driving Assistance System

ADSP Audio DSP, referring to the Cortex-A9 processor in the APE.

ADX Audio Demultiplexer Block, part of the Audio Hub used to demultiplex multiple audio streams.

AMBA Advanced Microcontroller Bus Architecture, a set of standard buses defined by ARM.

AMX Audio Multiplexer Block, part of the Audio Hub used to multiplex multiple audio streams together.

AO or AON Always-On power domain. This part of the chip is always powered on, even in the deepest sleep state, except

complete processor shutdown. See also SPE.

AON I/O rails I/Os in VDDIO_SYS, VDDIO_AO, and VDDIO_AO_HV serving the AON cluster logic

AONPG Always-On Non-Power Gated. Used to indicate when an AO partition has no power gating implemented.

AOPG Always-On Power Gated. Used to indicate when an AO partition has power gating implemented.

AOPM Always-On Cluster Power Management Module. PM module implements/manages the Cortex-R5 Power State

transitions. AOPM manages the SPE Cortex-R5 and its subsystem power states transitions.

AOTAG Always-On Thermal Alarm Generator

AOVC Always-On Voltage Controller

AP Applications Processor, refers to the Xavier device. Means the same as SoC.

APB AMBA Peripheral Bus, an ARM defined simple 32-bit single master bus for peripheral devices.

APE Audio Processing Engine

Aperture A named region of address space

APS Auxiliary processor subsystem. Refers to an implementation boundary that is shared across Cortex-R5 clusters

on the chip

NVIDIA Xavier Series System-on-Chip

Technical Reference Manual

Term Definition

ARM ARM is a company provides the CPU architectural specification for Xavier.

ARM is also Architecture Reference Manual, as in (the second ARM of) ARM ARM which defines the CPU

architecture.

AST Address Space Translator. A sub-unit associated with some of the embedded ARM cores that does address

translation from local addresses to system addresses along with appending some AXI attributes.

AXI AMBA Advanced eXtensible Interface, a more advanced bus than AHB defined as part of AMBA 3 by ARM.

AVIC ARM PL192 Vectored Interrupt Controller, used as the Cortex-R5 interrupt controller for all the Cortex-R5

processors (SPE, SCE, and BPMP).

Bayer A type of image sampling pattern invented by Dr. Bryce E. Bayer of Eastman Kodak. The pattern consists of

quads of pixels with two green samples, one red sample, and one blue sample:

BCT Boot Configuration Table. Stored on external boot device, contains config parameters for boot decisions

BIT Boot information Table. Maintained internally by Boot ROM in RAM for boot path/error tracking and logging

BKV Best Known Value. Configurations determined by system characterization

BOM Bottom of Memory, refers to the lowest address in an address map.

BPMP Boot and Power Management Processor, see the corresponding chapter.

BPMP-FW BPMP Firmware – This refers to the power management firmware that would be executed on BPMP (post-boot).

This is also stored in external boot media

BR Boot ROM (Power-on start boot code. Stored/burnt in chip IROM, executes from BPMP)

Brick I/O interface block with analog and other special functions

CAR Clock and Reset module, which controls clocks and resets to the various parts of Xavier.

Carmel NVIDIA proprietary CPU core that is ARMv8 compatible. This is used in the Xavier CCPLEX.

CBB Control Backbone

CCPLEX CPU complex – i.e., CPU subsystem

CDE Color Decompression Engine

CEC Consumer Electronics Control, a part of the HDMI interface specification used for sending device control

commands, often from a remote control.

CID Client ID

CIL Control and Interface Logic

Cold boot The SoC partition power transitions from OFF to ON with no previous state available. Software must construct all

states from scratch. Boot ROM is executed. DRAM is brought on-line.

CoT Chain-of-trust – a security term used to denote any code that is trusted because it is loaded securely from the root

of trust (Boot ROM)

CP Color Parser

C-PHY A MIPI standard physical layer that can carry CSI data; clocks are transmitted along with data. Data lanes are

three wires.

NVIDIA Xavier Series System-on-Chip

Technical Reference Manual

Term Definition

CPU Unless specified otherwise, CPU generally refers to the main Carmel CPUs

CRC Cyclic Redundancy Check

CSI MIPI Camera Serial Interface, a standard high-speed serial interface for connecting cameras to Xavier.

CUDA Compute Unified Device Architecture

CVC Central Voltage Controller

CV Cluster Computer Vision Cluster. A partition in Xavier which has NVDLA, PVA, and CVNAS.

CVNAS Computer Vision NoC and SRAM

CVNOC A sub-block within CVNAS–the NoC portion of CVNAS.

CVSRAM A sub-block within CVNAS–the memory storage portion of CVNAS.

CZ Controlled-output impedance MPIO pads.

DBC Dead Battery Charging

DBP Dead Battery Provisions

DBB Data Back-Bone

DCO Dynamic Code Optimization, a technique used by the Carmel CPU cores in Xavier to optimize the performance of

frequently executed ARM instructions. Refer to the CPU Complex chapter for more details.

DDA Digital Differential Analyzer, a technique commonly used in graphics for interpolation of variables over an interval

between start and end point, and also applied to other problems.

DDIC Display Driver IC

DFD Design for Debug

DFS Dynamic Frequency Scaling

DFT Design for Test

dGPU or DGPU Discrete GPU. Refers to an attached GPU which is external to the Xavier SoC, as opposed to the internal GPU.

DLA Deep Learning Accelerator

DLS Delayed Lock-Step

DMIC Digital microphone interface, supporting direct attach of PDM microphones.

DPD Deep Power Down. A mode in which the pad can tolerate VDD_CORE being turned off.

D-PHY A MIPI standard physical layer that can carry CSI data; clocks are transmitted separately from data. Data lanes

are two wires and clock lanes are two wires.

DRCM Debug Recovery Mode (also known as RCM-exit-to-JTAG)

DSI MIPI Display Serial Interface, a standard high-speed serial interface for connecting displays to Xavier.

DVC Dynamic Voltage Controller module

DVFS Dynamic Voltage and Frequency Scaling

EAVB Ethernet audio video bridging, and extension of the Ethernet standard supporting real-time streaming. More

recently referred to as Time-Sensitive Networking.

ECC Error Correction Code

eDP Embedded DisplayPort™

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NVIDIA Xavier SOC技术参考手册：系统架构与控制细节

Xavier_TRM_DP09253002.pdf

Nvidia_Xavier_SoC_datasheet.pdf

UG585 - Zynq-7000 SoC Technical Reference Manual (ver1.12.2)-技术参考手册.pdf

UserWarning: nn.init.xavier_uniform is now deprecated in favor of nn.init.xavier_uniform_. nn.init.xavier_uniform(m.weight, gain=nn.init.calculate_gain('relu'))

AttributeError: module 'keras.api._v1.keras.__internal__.legacy.layers' has no attribute 'xavier_initializer'

nn.init.xavier_uniform_(self.fc1.weight)

torch.nn.init.xavier_uniform_

nv_jetson_agx_xavier_developer_kit_user_guide.pdf

写一个用init.xavier_uniform_初始化化的模型

nn.init.xavier_uniform_的方差和均值默认是多少

if isinstance(layer, nn.Linear) or isinstance(layer, nn.Conv2d): nn.init.xavier_normal_(layer.weight.data)

nn.init.xavier_uniform_

torch.nn.init.xavier_uniform(w.weight)

nn.init.xavier_uniform_如何实现de

self.Phiweight = nn.Parameter(init.xavier_normal_(torch.Tensor(self.n_input, 1, self.patch_size, self.patch_size)))

embedding_xavier_uniform_(self.entity_embeddings)解释

if residual: if in_dim != out_dim: self.res_fc = nn.Linear(in_dim, num_heads * out_dim, bias=False) nn.init.xavier_normal_(self.res_fc.weight.data, gain=1.414) else: self.res_fc = None

tf.contrib.layers.xavier_initializer()转为TensorFlow2的代码

model = models.resnet18(pretrained=True) model.fc=nn.Linear(model.fc.in_features,38) nn.init.xavier_uniform_(model.fc.weight)

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AttributeError: module 'keras.api._v1.keras.internal.legacy.layers' has no attribute 'xavier_initializer'