Verilog设计基础与数字逻辑原理

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"《数字逻辑基础与Verilog设计》由斯蒂芬·布朗和兹沃尼科·瓦兰西奇合著，是电气和计算机工程专业入门级数字逻辑设计课程的理想教材。书中平衡了传统和现代设计方法，通过简单的逻辑电路介绍基本概念，然后使用CAD工具设计更复杂的电路。Verilog语言在全书的设计技术中扮演核心角色，同时提供了Altera的先进Max Plus II CAD系统（附带CD-ROM）和一系列逐步教程。" 《数字逻辑基础与Verilog设计》这本书深入浅出地讲解了数字逻辑的基础，旨在为学习者提供一个既包含古典方法又涵盖现代设计技术的全面视角。作者是来自多伦多大学电子与计算机工程系的专家，他们的专业知识和教学经验贯穿全书，确保了内容的权威性和实用性。 Verilog是一种硬件描述语言（HDL），在电子设计自动化（EDA）领域广泛使用，用于建模、仿真和综合数字电子系统。本书将Verilog作为核心工具，教授读者如何利用它来设计和验证数字逻辑电路。通过结合手动设计技巧和现代计算机辅助设计（CAD）工具，学生可以更好地理解和掌握逻辑设计的基本原理。书中的内容可能包括但不限于以下部分： 1. **数字逻辑基础**：介绍布尔代数，逻辑门（如AND、OR、NOT），以及组合逻辑电路的设计，如译码器、编码器、多路复用器等。 2. **时序逻辑**：探讨触发器、寄存器、计数器等时序电路的设计，强调状态机的概念。 3. **Verilog语法和编程**：讲解Verilog的语法结构，如模块定义、实例化、操作符、条件语句、循环等。 4. **硬件描述和仿真**：如何用Verilog描述数字系统，以及如何使用Max Plus II进行电路仿真和验证。 5. **综合和实现**：介绍如何将Verilog代码转换为实际硬件，包括逻辑优化和FPGA/CPLD的配置。 6. **案例研究和项目**：提供复杂电路设计实例，帮助学生将理论知识应用于实际问题解决。 7. **CAD工具使用**：通过附带的Altera Max Plus II教程，学生可以学习到如何使用这个流行的EDA工具进行设计和测试。本书不仅适合大学课堂使用，也适合作为自学资源，帮助工程师和爱好者提升数字逻辑和Verilog设计技能。通过深入学习，读者不仅能理解数字逻辑的基本原理，还能掌握Verilog语言在现代数字系统设计中的应用，为未来的职业生涯奠定坚实基础。

July 2, 2002 09:33 vra23151_tc Sheet number 4 Page number xviii black

xviii Contents

Problems 434

References 442

Chapter 8

Synchronous Sequential

Circuits 445

8.1 Basic Design Steps 447

8.1.1 State Diagram 447

8.1.2 State Table 449

8.1.3 State Assignment 449

8.1.4 Choice of Flip-Flops and Derivation

of Next-State and Output

Expressions 451

8.1.5 Timing Diagram 453

8.1.6 Summary of Design Steps 454

8.2 State-Assignment Problem 458

8.2.1 One-Hot Encoding 460

8.3 Mealy State Model 462

8.4 Design of Finite State Machines Using CAD

Tools 467

8.4.1 Verilog Code for Moore-Type

FSMs 467

8.4.2 Synthesis of Verilog Code 468

8.4.3 Simulating and Testing the Circuit 470

8.4.4 Alternative Styles of Verilog Code 471

8.4.5 Summary of Design Steps When Using

CAD Tools 473

8.4.6 Specifying the State Assignment in

Verilog Code 474

8.4.7 Speciﬁcation of Mealy FSMs Using

Verilog 475

8.5 Serial Adder Example 477

8.5.1 Mealy-Type FSM for Serial Adder 477

8.5.2 Moore-Type FSM for Serial Adder 479

8.5.3 Verilog Code for the Serial Adder 480

8.6 State Minimization 486

8.6.1 Partitioning Minimization

Procedure 486

8.6.2 Incompletely Speciﬁed FSMs 493

8.7 Design of a Counter Using the Sequential

Circuit Approach 495

8.7.1 State Diagram and State Table

for a Modulo-8 Counter 495

8.7.2 State Assignment 496

8.7.3 Implementation Using D-Type

Flip-Flops 497

8.7.4 Implementation Using JK-Type

Flip-Flops 498

8.7.5 Example—A Different Counter 502

8.8 FSM as an Arbiter Circuit 505

8.8.1 Implementation of the Arbiter

Circuit 508

8.8.2 Minimizing the Output Delays

for an FSM 511

8.8.3 Summary 511

8.9 Analysis of Synchronous Sequential

Circuits 512

8.10 Algorithmic State Machine (ASM)

Charts 516

8.11 Formal Model for Sequential Circuits 519

8.12 Concluding Remarks 521

Problems 521

References 525

Chapter 9

Asynchronous Sequential

Circuits 527

9.1 Asynchronous Behavior 528

9.2 Analysis of Asynchronous Circuits 531

9.3 Synthesis of Asynchronous Circuits 540

9.4 State Reduction 553

9.5 State Assignment 568

9.5.1 Transition Diagram 571

9.5.2 Exploiting Unspeciﬁed Next-State

Entries 574

9.5.3 State Assignment Using Additional

State Variables 578

9.5.4 One-Hot State Assignment 582

9.6 Hazards 584

9.6.1 Static Hazards 585

9.6.2 Dynamic Hazards 590

9.6.3 Signiﬁcance of Hazards 592

9.7 A Complete Design Example 592

9.7.1 The Vending-Machine Controller 592

9.8 Concluding Remarks 599

Problems 599

References 604

Chapter 10

Digital System Design 605

10.1 Building Block Circuits 606

10.1.1 Flip-Flops and Registers with Enable

Inputs 606

10.1.2 Shift Registers with Enable

Inputs 607

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Contents xix

10.1.3 Static Random Access Memory

(SRAM) 609

10.1.4 SRAM Blocks in PLDs 611

10.2 Design Examples 612

10.2.1 A Bit-Counting Circuit 612

10.2.2 ASM-Chart-Implied Timing

Information 613

10.2.3 Shift-and-Add Multiplier 618

10.2.4 Divider 623

10.2.5 Arithmetic Mean 631

10.2.6 Sort Operation 641

10.3 Clock Synchronization 653

10.3.1 Clock Skew 653

10.3.2 Flip-Flop Timing Parameters 655

10.3.3 Asynchronous Inputs to Flip-Flops 656

10.3.4 Switch Debouncing 657

10.4 Concluding Remarks 659

Problems 659

References 663

Chapter 11

Testing of Logic Circuits 665

11.1 Fault Model 666

11.1.1 Stuck-at Model 666

11.1.2 Single and Multiple Faults 667

11.1.3 CMOS Circuits 667

11.2 Complexity of a Test Set 667

11.3 Path Sensitizing 669

11.3.1 Detection of a Speciﬁc Fault 671

11.4 Circuits with Tree Structure 673

11.5 Random Tests 674

11.6 Testing of Sequential Circuits 677

11.6.1 Design for Testability 677

11.7 Built-in Self-Test 681

11.7.1 Built-in Logic Block Observer 685

11.7.2 Signature Analysis 687

11.7.3 Boundary Scan 688

11.8 Printed Circuit Boards 688

11.8.1 Testing of PCBs 690

11.8.2 Instrumentation 691

11.9 Concluding Remarks 692

Problems 692

References 695

Appendix A

Verilog Reference 697

A.1 Documentation in Verilog Code 699

A.2 White Space 699

A.3 Signals in Verilog Code 699

A.4 Identiﬁer Names 699

A.5 Signal Values, Numbers, and Parameters 700

A.6 Net and Variable Types 701

A.6.1 Nets 701

A.6.2 Variables 702

A.6.3 Memories 703

A.7 Operators 703

A.8 Verilog Module 705

A.9 Gate Instantiations 706

A.10 Concurrent Statements 708

A.10.1 Continuous Assignments 709

A.10.2 Using Parameters 710

A.11 Procedural Statements 711

A.11.1 Always and Initial Blocks 711

A.11.2 The If-Else Statement 713

A.11.3 Statement Ordering 714

A.11.4 The Case Statement 715

A.11.5 Casex and Casez Statements 717

A.11.6 Loop Statements 717

A.11.7 Blocking versus Non-blocking

Assignments for Combinational

Circuits 721

A.12 Using Subcircuits 721

A.12.1 Subcircuit Parameters 723

A.12.2 Verilog 2001 Generate Capability 725

A.13 Functions and Tasks 726

A.14 Sequential Circuits 730

A.14.1 A Gated D Latch 730

A.14.2 D Flip-Flop 730

A.14.3 Flip-Flops with Reset 731

A.14.4 Instantiating a Flip-Flop from a

Library 732

A.14.5 Registers 733

A.14.6 Shift Registers 734

A.14.7 Counters 735

A.14.8 An Example of a Sequential

Circuit 736

A.14.9 Moore-Type Finite State

Machines 737

A.14.10 Mealy-Type Finite State

Machines 739

A.15 Guidelines for Writing Verilog Code 742

A.16 MAX+PlusII Verilog Support 745

A.16.1 Limitations in MAX+PlusII 745

A.17 Concluding Remarks 746

References 746

July 2, 2002 09:33 vra23151_tc Sheet number 6 Page number xx black

xx Contents

Appendix B

Tutorial 1 747

B.1 Introduction 748

B.1.1 Getting Started 748

B.2 Design Entry Using Schematic

Capture 751

B.2.1 Specifying the Project Name 752

B.2.2 Using the Graphic Editor 752

B.2.3 Synthesizing a Circuit from the

Schematic 758

B.2.4 Performing Functional Simulation 759

B.2.5 Using the Message Processor to Locate

and Fix Errors 763

B.3 Design Entry Using Verilog 765

B.3.1 Specifying the Project Name 765

B.3.2 Using the Text Editor 765

B.3.3 Synthesizing a Circuit from the Verilog

Code 767

B.3.4 Performing Functional Simulation 767

B.3.5 Using the Message Processor to Debug

Verilog Code 768

B.4 Design Entry Using Truth Tables 768

B.4.1 Using the Waveform Editor 769

B.4.2 Create the Timing Diagram 769

B.4.3 Synthesizing a Circuit from the

Waveforms 770

B.5 Mixing Design-Entry Methods 772

B.5.1 Creating a Schematic that Includes a

Truth Table 772

B.5.2 Synthesizing and Simulating a Circuit

from the Schematic 774

B.5.3 Using the Hierarchy Display 775

B.5.4 Concluding Remarks 775

Appendix C

Tutorial 2 777

C.1 Implementing a Circuit

in a MAX 7000 CPLD 778

C.1.1 Using the Compiler 779

C.1.2 Selecting a Chip 780

C.1.3 Viewing the Logic Synthesis

Options 781

C.1.4 Examining the Implemented

Circuit 782

C.1.5 Running the Timing Simulator 783

C.1.6 Using the Floorplan Editor 784

C.2 Implementing a Circuit in a FLEX 10K

FPGA 787

C.3 Downloading a Circuit into a Device 789

C.4 Making Pin Assignments 790

C.4.1 Assigning Signals to Pins in the

Floorplan Editor 792

C.4.2 Making Pin Assignments

Permanent 794

C.5 Concluding Remarks 795

Appendix D

Tutorial 3 797

D.1 Design Using Verilog Code 798

D.1.1 The Ripple-Carry Adder Code 798

D.1.2 Using the Timing Analyzer

Module 801

D.2 Using an LPM Module 802

D.3 Design of a Sequential Circuit 806

D.3.1 Using the Graphic Editor 806

D.3.2 Synthesizing a Circuit and Using the

Timing Simulator 812

D.3.3 Using the Timing Analyzer 813

D.3.4 Using Verilog Code 814

D.4 Design of a Finite State Machine 815

D.4.1 Implementation in a CPLD 815

D.4.2 Implementation in an FPGA 816

D.5 Concluding Remarks 819

Appendix E

Commercial Devices 821

E.1 Simple PLDs 822

E.1.1 The 22V10 PAL Device 822

E.2 Complex PLDs 824

E.2.1 Altera MAX 7000 825

E.3 Field-Programmable Gate Arrays 826

E.3.1 Altera FLEX 10K 827

E.3.2 Xilinx XC4000 830

E.3.3 Altera APEX 20K 831

E.3.4 Altera Stratix 832

E.3.5 Xilix Virtex 834

E.4 Transistor-Transistor Logic 835

E.4.1 TTL Circuit Families 836

References 837

Index 838

June 10, 2002 11:03 vra23151_ch01 Sheet number 2 Page number 2 black

2 CHAPTER 1

•

Design Concepts

This book is about logic circuits—the circuits from which computers are built. Proper understanding of

logic circuits is vital for today’s electrical and computer engineers. These circuits are the key ingredient of

computers and are also used in many other applications. They are found in commonly used products, such as

digital watches, various household appliances, CD players, and electronic games, as well as in large systems,

such as the equipment for telephone and television networks.

The material in this book will introduce the reader to the many issues involved in the design of logic

circuits. It explains the key ideas with simple examples and shows how complex circuits can be derived from

elementary ones. We cover the classical theory used in the design of logic circuits in great depth because it

provides the reader with an intuitive understanding of the nature of such circuits. But throughout the book we

also illustrate the modern way of designing logic circuits, using sophisticated computer aided design (CAD)

software tools. The CAD methodology adopted in the book is based on the industry-standard design language

called Verilog. Design with Verilog is ﬁrst introduced in Chapter 2, and usage of Verilog and CAD tools is

an integral part of each chapter in the book.

Logic circuits are implemented electronically, using transistors on an integrated circuit chip. With modern

technology it is possible to fabricate chips that contain tens of millions of transistors, as in the case of computer

processors. The basic building blocks for such circuits are easy to understand, but there is nothing simple

about a circuit that contains tens of millions of transistors. The complexity that comes with the large size of

logic circuits can be handled successfully only by using highly organized design techniques. We introduce

these techniques in this chapter, but ﬁrst we brieﬂy describe the hardware technology used to build logic

circuits.

1.1 Digital Hardware

Logic circuits are used to build computer hardware, as well as many other types of products.

All such products are broadly classiﬁedas digital hardware. The reasonthat the name digital

is used will become clear later in the book—it derives from the way in which information

is represented in computers, as electronic signals that correspond to digits of information.

The technology used to build digital hardware has evolved dramatically over the past

four decades. Until the 1960s logic circuits were constructed with bulky components, such

as transistors and resistors that came as individual parts. The advent of integrated circuits

made it possible to place a number of transistors, and thus an entire circuit, on a single

chip. In the beginning these circuits had only a few transistors, but as the technology

improved they became larger. Integrated circuit chips are manufactured on a silicon wafer,

such as the one shown in Figure 1.1. The wafer is cut to produce the individual chips,

which are then placed inside a special type of chip package. By 1970 it was possible to

implement all circuitry needed to realize a microprocessor on a single chip. Although early

microprocessors had modest computing capability by today’s standards, they opened the

door for the information processing revolution by providing the means for implementation

of affordable personal computers. About 30 years ago Gordon Moore, chairman of Intel

Corporation, observed that integrated circuit technology was progressing at an astounding

rate, doubling the number of transistors that could be placed on a chip every 1.5 to 2 years.

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