STM32mp157a数据手册：详尽指南及使用说明（2022年2月版）

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The STM32MP157a is a powerful and versatile microprocessor designed for applications requiring high performance and efficiency. The STM32MP157a data sheet provides comprehensive information on the various features and capabilities of this advanced Arm-based 32-bit MPU. The STM32MP157a family includes a range of microprocessors with different memory sizes, packages, and peripherals, making it suitable for a wide variety of applications. Whether you need a compact and energy-efficient solution or a high-performance processor with extensive connectivity options, the STM32MP157a has you covered. This reference manual is essential for application developers looking to harness the full potential of the STM32MP157a. It covers all aspects of using the microprocessor's memory and peripherals, including detailed instructions on configuration and optimization. For additional details on ordering information, mechanical specifications, and electrical device characteristics, developers are encouraged to consult the accompanying datasheets. These documents provide valuable insights into the physical characteristics of the STM32MP157a, helping developers make informed decisions when designing their applications. In conclusion, the STM32MP157a data sheet is a comprehensive resource for developers seeking to leverage the advanced capabilities of this versatile microprocessor. By following the guidelines outlined in this manual and referencing the accompanying datasheets, developers can confidently design and implement successful applications using the STM32MP157a.

Contents RM0436

16/4017 RM0436 Rev 2

10.7.37 RCC PLL2 Clock Spreading Generator Register (RCC_PLL2CSGR) . 676

10.7.38 RCC PLL3 Control Register (RCC_PLL3CR) . . . . . . . . . . . . . . . . . . . 677

10.7.39 RCC PLL3 Configuration Register 1 (RCC_PLL3CFGR1) . . . . . . . . . 679

10.7.40 RCC PLL3 Configuration Register 2 (RCC_PLL3CFGR2) . . . . . . . . . 680

10.7.41 RCC PLL3 Fractional Register (RCC_PLL3FRACR) . . . . . . . . . . . . . 681

10.7.42 RCC PLL3 Clock Spreading Generator Register (RCC_PLL3CSGR) . 682

10.7.43 RCC PLL4 Control Register (RCC_PLL4CR) . . . . . . . . . . . . . . . . . . . 682

10.7.44 RCC PLL4 Configuration Register 1 (RCC_PLL4CFGR1) . . . . . . . . . 684

10.7.45 RCC PLL4 Configuration Register 2 (RCC_PLL4CFGR2) . . . . . . . . . 685

10.7.46 RCC PLL4 Fractional Register (RCC_PLL4FRACR) . . . . . . . . . . . . . 685

10.7.47 RCC PLL4 Clock Spreading Generator Register (RCC_PLL4CSGR) . 686

10.7.48 RCC I2C1,2 Kernel Clock Selection Register (RCC_I2C12CKSELR) . 687

10.7.49 RCC I2C3,5 Kernel Clock Selection Register (RCC_I2C35CKSELR) . 689

10.7.50 RCC I2C4, 6 kernel clock selection register

(RCC_I2C46CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

10.7.51 RCC SAI1 Kernel Clock Selection Register (RCC_SAI1CKSELR) . . . 691

10.7.52 RCC SAI2 Kernel Clock Selection Register (RCC_SAI2CKSELR) . . . 692

10.7.53 RCC SAI3 Kernel Clock Selection Register (RCC_SAI3CKSELR) . . . 693

10.7.54 RCC SAI4 Kernel Clock Selection Register (RCC_SAI4CKSELR) . . . 693

10.7.55 RCC SPI/I2S1 Kernel Clock Selection Register

(RCC_SPI2S1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

10.7.56 RCC SPI/I2S2,3 Kernel Clock Selection Register

(RCC_SPI2S23CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

10.7.57 RCC SPI4,5 Kernel Clock Selection Register (RCC_SPI45CKSELR) 696

10.7.58 RCC SPI6 Kernel Clock Selection Register (RCC_SPI6CKSELR) . . . 697

10.7.59 RCC USART6 Kernel Clock Selection Register

(RCC_UART6CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

10.7.60 RCC UART2,4 Kernel Clock Selection Register

(RCC_UART24CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

10.7.61 RCC UART3,5 Kernel Clock Selection Register

(RCC_UART35CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

10.7.62 RCC UART7,8 Kernel Clock Selection Register

(RCC_UART78CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

10.7.63 RCC USART1 Kernel Clock Selection Register

(RCC_UART1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

10.7.64 RCC SDMMC1&2 Kernel Clock Selection Register

(RCC_SDMMC12CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

10.7.65 RCC SDMMC3 Kernel Clock Selection Register

(RCC_SDMMC3CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

10.7.66 RCC Ethernet Kernel Clock Selection Register (RCC_ETHCKSELR) 705

RM0436 Rev 2 17/4017

RM0436 Contents

10.7.67 RCC QUADSPI Kernel Clock Selection Register

(RCC_QSPICKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

10.7.68 RCC FMC Kernel Clock Selection Register (RCC_FMCCKSELR) . . . 707

10.7.69 RCC FDCAN Kernel Clock Selection Register

(RCC_FDCANCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

10.7.70 RCC SPDIFRX Kernel Clock Selection Register

(RCC_SPDIFCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

10.7.71 RCC CEC Kernel Clock Selection Register (RCC_CECCKSELR) . . . 710

10.7.72 RCC USB Kernel Clock Selection Register (RCC_USBCKSELR) . . . 711

10.7.73 RCC RNG1 Kernel Clock Selection Register (RCC_RNG1CKSELR) . 712

10.7.74 RCC RNG2 Kernel Clock Selection Register (RCC_RNG2CKSELR) . 713

10.7.75 RCC Common Peripheral Clock Selection Register

(RCC_CPERCKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

10.7.76 RCC STGEN Clock Selection Register (RCC_STGENCKSELR) . . . . 715

10.7.77 RCC DDR Interface Control Register (RCC_DDRITFCR) . . . . . . . . . . 716

10.7.78 RCC DSI Kernel Clock Selection Register (RCC_DSICKSELR) . . . . . 721

10.7.79 RCC ADC Kernel Clock Selection Register (RCC_ADCCKSELR) . . . 722

10.7.80 RCC LPTIM4 & 5 Kernel Clock Selection Register

(RCC_LPTIM45CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

10.7.81 RCC LPTIM2 & 3 Kernel Clock Selection Register

(RCC_LPTIM23CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

10.7.82 RCC LPTIM1 Kernel Clock Selection Register

(RCC_LPTIM1CKSELR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

10.7.83 RCC Boot Control Register (RCC_MP_BOOTCR) . . . . . . . . . . . . . . . 726

10.7.84 RCC Stop Request Set Register (RCC_MP_SREQSETR) . . . . . . . . . 727

10.7.85 RCC Stop Request Clear Register (RCC_MP_SREQCLRR) . . . . . . . 728

10.7.86 RCC Global Control Register (RCC_MP_GCR) . . . . . . . . . . . . . . . . . 729

10.7.87 RCC application Reset Control Register (RCC_MP_APRSTCR) . . . . 730

10.7.88 RCC Application Reset Status Register (RCC_MP_APRSTSR) . . . . . 731

10.7.89 RCC Backup Domain Control Register (RCC_BDCR) . . . . . . . . . . . . 732

10.7.90 RCC Reset Duration and LSI Control Register (RCC_RDLSICR) . . . . 733

10.7.91 RCC Clock Source Interrupt Enable Register (RCC_MP_CIER) . . . . 736

10.7.92 RCC Clock Source Interrupt Flag Register (RCC_MP_CIFR) . . . . . . . 738

10.7.93 RCC Clock Source Interrupt Enable Register (RCC_MC_CIER) . . . . 739

10.7.94 RCC Clock Source Interrupt Flag Register (RCC_MC_CIFR) . . . . . . . 742

10.7.95 RCC PWR_LP Delay Control Register (RCC_PWRLPDLYCR) . . . . . 744

10.7.96 RCC APB1 Peripheral Reset Set Register (RCC_APB1RSTSETR) . . 744

10.7.97 RCC APB1 Peripheral Reset Clear Register (RCC_APB1RSTCLRR) 748

10.7.98 RCC APB2 Peripheral Reset Set Register (RCC_APB2RSTSETR) . . 751

Contents RM0436

18/4017 RM0436 Rev 2

10.7.99 RCC APB2 Peripheral Reset Clear Register (RCC_APB2RSTCLRR) 752

10.7.100 RCC APB3 Peripheral Reset Set Register (RCC_APB3RSTSETR) . . 754

10.7.101 RCC APB3 Peripheral Reset Clear Register (RCC_APB3RSTCLRR) 757

10.7.102 RCC AHB2 Peripheral Reset Set Register (RCC_AHB2RSTSETR) . . 759

10.7.103 RCC AHB2 Peripheral Reset Clear Register (RCC_AHB2RSTCLRR) 761

10.7.104 RCC AHB3 Peripheral Reset Set Register (RCC_AHB3RSTSETR) . . 763

10.7.105 RCC AHB3 Peripheral Reset Clear Register (RCC_AHB3RSTCLRR) 765

10.7.106 RCC AHB4 Peripheral Reset Set Register (RCC_AHB4RSTSETR) . . 767

10.7.107 RCC AHB4 Peripheral Reset Clear Register (RCC_AHB4RSTCLRR) 769

10.7.108 RCC APB4 Peripheral Reset Set Register (RCC_APB4RSTSETR) . . 771

10.7.109 RCC APB4 Peripheral Reset Clear Register (RCC_APB4RSTCLRR) 771

10.7.110 RCC APB5 Peripheral Reset Set Register (RCC_APB5RSTSETR) . . 772

10.7.111 RCC APB5 Peripheral Reset Clear Register (RCC_APB5RSTCLRR) 774

10.7.112 RCC AHB5 Peripheral Reset Set Register (RCC_AHB5RSTSETR) . . 775

10.7.113 RCC AHB5 Peripheral Reset Clear Register (RCC_AHB5RSTCLRR) 776

10.7.114 RCC AHB6 Peripheral Reset Set Register (RCC_AHB6RSTSETR) . . 777

10.7.115 RCC AHB6 Peripheral Reset Clear Register (RCC_AHB6RSTCLRR) 779

10.7.116 RCC AHB6 Secure Peripheral Reset Set Register

(RCC_TZAHB6RSTSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

10.7.117 RCC AHB6 Secure Peripheral Reset Clear Register

(RCC_TZAHB6RSTCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

10.7.118 RCC Global Reset Control Set Register

(RCC_MP_GRSTCSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

10.7.119 RCC APB1 Peripheral Enable For MPU Set Register

(RCC_MP_APB1ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

10.7.120 RCC APB1 Peripheral Enable For MCU Set Register

(RCC_MC_APB1ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

10.7.121 RCC APB1 Periph. Enable For MPU Clear Register

(RCC_MP_APB1ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

10.7.122 RCC APB1 Periph. Enable For MCU Clear Register

(RCC_MC_APB1ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796

10.7.123 RCC APB2 Periph. Enable For MPU Set Register

(RCC_MP_APB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

10.7.124 RCC APB2 Periph. Enable For MCU Set Register

(RCC_MC_APB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

10.7.125 RCC APB2 Periph. Enable For MPU Clear Register

(RCC_MP_APB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

10.7.126 RCC APB2 Periph. Enable For MCU Clear Register

(RCC_MC_APB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

10.7.127 RCC APB3 Periph. Enable For MPU Set Register

(RCC_MP_APB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

RM0436 Rev 2 19/4017

RM0436 Contents

10.7.128 RCC APB3 Periph. Enable For MCU Set Register

(RCC_MC_APB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

10.7.129 RCC APB3 Periph. Enable For MPU Clear Register

(RCC_MP_APB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

10.7.130 RCC APB3 Periph. Enable For MCU Clear Register

(RCC_MC_APB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

10.7.131 RCC APB4 Periph. Enable For MCU Set Register

(RCC_MC_APB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

10.7.132 RCC APB4 Periph. Enable For MPU Set Register

(RCC_MP_APB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

10.7.133 RCC APB4 Periph. Enable For MCU Clear Register

(RCC_MC_APB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

10.7.134 RCC APB4 Periph. Enable For MPU Clear Register

(RCC_MP_APB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

10.7.135 RCC APB5 Periph. Enable For MCU Set Register

(RCC_MC_APB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

10.7.136 RCC APB5 Periph. Enable For MPU Set Register

(RCC_MP_APB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

10.7.137 RCC APB5 Periph. Enable For MCU Clear Register

(RCC_MC_APB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

10.7.138 RCC APB5 Periph. Enable For MPU Clear Register

(RCC_MP_APB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

10.7.139 RCC AHB5 Periph. Enable For MCU Set Register

(RCC_MC_AHB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

10.7.140 RCC AHB5 Periph. Enable For MPU Set Register

(RCC_MP_AHB5ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

10.7.141 RCC AHB5 Periph. Enable For MCU Clear Register

(RCC_MC_AHB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

10.7.142 RCC AHB5 Periph. Enable For MPU Clear Register

(RCC_MP_AHB5ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

10.7.143 RCC AHB6 Periph. Enable For MPU Set Register

(RCC_MP_AHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

10.7.144 RCC AHB6 Periph. Enable For MCU Set Register

(RCC_MC_AHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

10.7.145 RCC AHB6 Periph. Enable For MPU Clear Register

(RCC_MP_AHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

10.7.146 RCC AHB6 Periph. Enable For MCU Clear Register

(RCC_MC_AHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

10.7.147 RCC AHB6 Secure Periph. Enable For MPU Set Register

(RCC_MP_TZAHB6ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

10.7.148 RCC AHB6 Secure Periph. Enable For MPU Clear Register

(RCC_MP_TZAHB6ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

Contents RM0436

20/4017 RM0436 Rev 2

10.7.149 RCC AHB2 Periph. Enable For MPU Set Register

(RCC_MP_AHB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

10.7.150 RCC AHB2 Periph. Enable For MCU Set Register

(RCC_MC_AHB2ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

10.7.151 RCC AHB2 Periph. Enable For MPU Clear Register

(RCC_MP_AHB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

10.7.152 RCC AHB2 Periph. Enable For MCU Clear Register

(RCC_MC_AHB2ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

10.7.153 RCC AHB3 Periph. Enable For MPU Set Register

(RCC_MP_AHB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

10.7.154 RCC AHB3 Periph. Enable For MCU Set Register

(RCC_MC_AHB3ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

10.7.155 RCC AHB3 Periph. Enable For MPU Clear Register

(RCC_MP_AHB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

10.7.156 RCC AHB3 Periph. Enable For MCU Clear Register

(RCC_MC_AHB3ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

10.7.157 RCC AHB4 Periph. Enable For MPU Set Register

(RCC_MP_AHB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

10.7.158 RCC AHB4 Periph. Enable For MCU Set Register

(RCC_MC_AHB4ENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

10.7.159 RCC AHB4 Periph. Enable For MPU Clear Register

(RCC_MP_AHB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

10.7.160 RCC AHB4 Periph. Enable For MCU Clear Register

(RCC_MC_AHB4ENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

10.7.161 RCC AXI Periph. Enable For MCU Set Register

(RCC_MC_AXIMENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

10.7.162 RCC AXI Periph. Enable For MCU Clear Register

(RCC_MC_AXIMENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

10.7.163 RCC MLAHB Periph. Enable For MCU Set Register

(RCC_MC_MLAHBENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877

10.7.164 RCC MLAHB Periph. Enable For MCU Clear Register

(RCC_MC_MLAHBENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878

10.7.165 RCC MLAHB Periph. Enable For MPU Set Register

(RCC_MP_MLAHBENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

10.7.166 RCC MLAHB Periph. Enable For MPU Clear Register

(RCC_MP_MLAHBENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

10.7.167 RCC APB1 Sleep Clock Ena. For MPU Set Register

(RCC_MP_APB1LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

10.7.168 RCC APB1 Sleep Clock Ena. For MCU Set Register

(RCC_MC_APB1LPENSETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885

10.7.169 RCC APB1 Sleep Clock Ena. MPU Clear Register

(RCC_MP_APB1LPENCLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890

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