Xilinx UltraScale架构SelectIO资源详解：v1.15用户指南

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本资源是Xilinx针对其UltraScale架构的SelectIO资源英文手册（User Guide UG571 v1.15），发布日期为2023年8月30日。UltraScale架构是Xilinx推出的一款高性能FPGA平台，SelectIO是其中一项关键特性，它提供了高效、灵活的I/O接口解决方案。该手册详尽介绍了SelectIO的功能、配置指南、内部逻辑接口设计以及引脚端口的使用方法。首先，章节一“SelectIO Interface Resources”阐述了UltraScale架构的特点，对比了与前代产品的区别，强调了SelectIO技术在I/O性能和灵活性方面的提升。这一章节着重于SelectIO接口的通用指导原则，包括DCI（Data Compression Interface）的特性和仅在HPI/O Banks中可用的特性。 DCI部分解释了这一技术如何通过压缩数据传输来减少带宽占用和提高效率。Uncalibrated Input Termination则涉及I/O Bank中的未校准输入终止设置，这对于信号完整性优化至关重要。手册还深入剖析了SelectIO Interface Primitives，即构成SelectIO基础的硬件模块，它们是实现高级I/O功能的基础组件。接着，SelectIO Interface Attributes部分详细描述了如何配置这些接口以满足不同的应用场景需求，包括时序参数、驱动能力、输入/输出缓冲等，确保系统设计的兼容性和性能最大化。此外，手册还可能包含了关于SelectIO在Vivado工具中的集成以及如何利用这些资源进行FPGA设计的实用指南。总体来说，这份文档为开发者提供了全面的指导，无论是初次接触UltraScale架构的用户，还是经验丰富的FPGA设计师，都能从中获益良多，以便充分利用SelectIO资源来构建高性能和低功耗的系统设计。随着AMD的适应性计算策略，文档也体现了对包容性语言的重视，旨在消除可能存在的偏见和排除性术语，以创建一个更加友好和包容的开发环境。

UltraScale Architecture SelectIO Resources 16

UG571 (v1.15) August 30, 2023

Chapter1: SelectIO Interface Resources

CAUTION! Incorrect V

CCO

voltages can result in loss of functionality or damage the device.

In HR I/O banks, if the I/O standard voltage requirement is 1.8V, but a V

CCO

voltage of

2.5V is applied, the device automatically enters an over-voltage protection mode.

Reconfiguring the device with the correct V

CCO

voltage level restores normal operation.

REF

Single-ended I/O standards with a differential input buffer require an input reference

voltage (V

REF

). When V

REF

is required within an I/O bank, you can use either the dedicated

REF

pin as a V

REF

supply input (external) or an internally generated V

REF

(INTERNAL_VREF or

REF

scan (HP I/O banks only)). An internally generated reference voltage is enabled by

using the INTERNAL_VREF constraint. Output-only IOBs do not require a V

REF

INTERNAL_VREF because only the receive portion of an IOB leverages the input reference

voltage. For more information on this constraint, see SelectIO Interface Attributes and

Constraints, page 57.

IMPORTANT: In banks where the input I/O standard has an input reference voltage requirement and

uses an internally generated V

REF

(INTERNAL_VREF or V

REF

scan), connect the dedicated V

REF

pin to

GND with a 500



or 1 K



resistor.

In banks where the I/O standard does not have an input reference voltage requirement,

connect the dedicated V

REF

pin to GND (with a 500 or 1K resistor), or leave it floating.

The internal V

REF

scan feature is available in HP I/O banks to account for process variations

and system considerations.

CCAUX

The global auxiliary (V

CCAUX

) supply rail primarily provides power to the interconnect logic

of the various blocks inside the device. In the I/O banks, V

CCAUX

is also used to power input

buffer circuits for some of the I/O standards. These include some of the single-ended I/O

standards at or below 1.8V, and also some of the 2.5V standards (HR I/O banks only).

Additionally, the V

CCAUX

rail provides power to the differential input buffer circuits used for

most of the differential and V

REF

I/O standards.

The power supply requirements, including power-on and power-off sequencing, are

described in the UltraScale device data sheets [Ref 2].

CCAUX_IO

The auxiliary I/O (V

CCAUX_IO

) voltage supply rail provides power to the I/O circuitry.

CCAUX_IO

should only be powered by 1.8V.

CCINT_IO

This is an internal supply for I/O banks. Connect to the V

CCINT

voltage supply rail.

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UltraScale Architecture SelectIO Resources 17

UG571 (v1.15) August 30, 2023

Chapter1: SelectIO Interface Resources

State of I/Os During and After Configuration

UltraScale devices have pins dedicated to the configuration functions contained in I/O

bank 0. There are also I/O pins in bank 65 (multi-function configuration bank) known as

multi-function or multipurpose pins that can be used for configuration and converted to

programmable I/O pins after configuration is complete. Additionally, during configuration

of devices with multiple super logic regions (SLRs), the pins in bank 60 and bank 70 have

restrictions similar to the multi-function pins. The restrictions on these banks are required

even though they are not configuration banks.

During configuration, I/O drivers are 3-stated in all banks except the banks used for

configuration (bank 0 and bank 65) and the aforementioned bank 60 and bank 70 in

devices with multiple SLRs. During configuration (until the applications settings take over),

all HP I/O banks use the default IOSTANDARD = LVCMOS18, SLEW = FAST, and

DRIVE = 12 mA setting. The corresponding setting in HR I/O banks is

IOSTANDARD = LVCMOS25, SLEW = FAST, and DRIVE = 12 mA. After configuration, the

unconfigured I/Os have 3-stated drivers and the pads are weakly pulled-down.

In devices where bank 65 (all devices) and bank 70 (only devices with multiple SLRs) are HR

I/O banks and configured with a V

CCO

requirement 1.8V, the inputs can have 0-1-0

transition to the interconnect logic during configuration if the input is tied to a 0 or floated

and the configuration voltage is 2.5V. For further details, see the UltraScale Architecture

Configuration User Guide (UG570) [Ref 4].

UltraScale (not UltraScale+) devices with multiple SLRs can have the weak pull-up

temporarily enabled on I/Os in the slave SLR during the configuration sequence (between

power on and assertion of the INIT_B configuration signal). In some boards, this can cause

an undesired 0-1-0 transition on I/O in the slave SLR. It is recommended that any I/O pins

in the slave SLR sensitive to a 0-1-0 transition during configuration be connected to I/Os in

the master SLR or include external pull-downs of 1 k or stronger to the pin.

Send Feedback

UltraScale Architecture SelectIO Resources 18

UG571 (v1.15) August 30, 2023

Chapter1: SelectIO Interface Resources

DCI—Only Available in the HP I/O Banks

Introduction

As device footprints increase and system clock speeds get faster, PC board design and

manufacturing becomes more difficult. With ever faster edge rates, maintaining signal

integrity becomes a critical issue. PC board traces must be properly terminated to avoid

reflections or ringing.

To terminate a trace, resistors are traditionally added to make the output and/or input

match the impedance of the receiver or driver to the impedance of the trace. However, due

to increased device I/Os, adding resistors close to the device pins increases the board area

and component count, and can in some cases be physically impossible. To address these

issues and to achieve better signal integrity, AMD developed the digitally controlled

impedance (DCI) technology.

Depending on the I/O standard, DCI can either control the output impedance of a driver, or

add a parallel termination present at the receiver, with the goal of accurately matching the

characteristic impedance of the transmission line. DCI actively adjusts these impedances

inside the I/O to calibrate to an external precision reference resistor placed on the VRP pin.

This compensates for changes in I/O impedance due to process variation. It also

continuously adjusts the impedances to compensate for variations of temperature and

supply voltage fluctuations. Many designs require the use of multiple DCI reference VRP

pins. In these scenarios, a unique reference resistor is required for each VRP pin.

IMPORTANT: For all DCI I/O standards, the external reference resistor (R

VRP

) should be 240



For the I/O standards with controlled parallel termination, DCI provides the parallel

termination for receivers. This eliminates the need for termination resistors on the board,

reduces board routing difficulties and component count, and improves signal integrity by

eliminating stub reflection. Stub reflection occurs when termination resistors are located

too far from the end of the transmission line. With DCI, the termination resistors are as

close as possible to the output driver or the input buffer, thus, eliminating stub reflections.

The exact value of the termination resistors is determined by the ODT attribute for

controlled parallel termination. The exact driver termination value is determined by the

OUTPUT_IMPEDANCE attribute for the controlled impedance driver. DCI is only available in

HP I/O banks. DCI is not available in HR I/O banks.

DCI uses one multipurpose reference VRP pin in each I/O bank to control the impedance of

the driver or the parallel-termination value for all of the I/Os of that bank.

IMPORTANT: When using DCI standards, the VRP pin must be terminated to GND by a reference

resistor. The value of the resistor should be 240



Send Feedback

UltraScale Architecture SelectIO Resources 19

UG571 (v1.15) August 30, 2023

Chapter1: SelectIO Interface Resources

To implement DCI in a design:

1. Assign one of the DCI I/O standards in an HP I/O bank (see Tabl e 1- 3).

2. Connect the VRP multi-function pin to a precision resistor (240) tied to GND.

3. Set the desired termination value using the ODT attribute for all applicable I/Os with

controlled parallel terminations. Set the termination value using the

OUTPUT_IMPEDANCE attribute for all applicable I/Os with a controlled impedance

driver.

If several I/O banks in the same I/O bank column are using DCI, the internal VRP node can

be cascaded so that only one VRP pin for all of the I/O banks in the entire I/O column is

required to be connected to a precision resistor. This option is called DCI cascading as is

detailed in DCI Cascading. This section also describes how to determine if I/O banks share

the same I/O bank column. If DCI I/O standards are not used in the bank, the VRP pin is

available as a standard I/O pin. The UltraScale and UltraScale+ FPGAs Packaging and

Pinouts Product Specification (UG575) [Ref 3] gives detailed pin descriptions.

DCI adjusts the impedance of the I/O by selectively turning resistors in the I/Os on or off.

The adjustment starts during the device start-up sequence. By default, the DONE pin does

not transition High until the first part of the impedance adjustment process is completed.

The DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the RST

input to the DCIRESET primitive while the device is operating resets the DCI state machine

and restarts the calibration process. All I/Os using DCI are unavailable until the LOCKED

output from the DCIRESET block is asserted. This functionality is useful in applications

where the temperature and/or supply voltage changes significantly from device power-up

to the nominal operating condition.

For controlled impedance output drivers, the exact value of the driver terminations is

determined by the OUTPUT_IMPEDANCE attribute. For the I/O standards that support

parallel termination, DCI creates a Thevenin equivalent, or split-termination resistance to

the V

CCO

/2 voltage level, or a single-termination resistance to the V

CCO

voltage level. The

value of split-termination resistors are determined by the ODT attribute. For POD and HSUL

standards, DCI supports single termination to V

CCO

. The value of the termination resistance

is determined by the ODT attribute.

Match_cycle Configuration Option

Match_cycle is a configuration option that can halt the start-up sequence at the end of the

device configuration sequence until the DCI logic has performed the first match

(calibration) to the external reference resistor. This option is also sometimes referred to as

DCI match.

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UltraScale Architecture SelectIO Resources 20

UG571 (v1.15) August 30, 2023

Chapter1: SelectIO Interface Resources

DCIUpdateMode Configuration Option

DCIUpdateMode is a configuration option that can override control of how often the DCI

circuit updates the impedance matching to the VRP reference resistor. This option defaults

to ASREQUIRED in the AMD implementation tools. The settings for the DCIUpdateMode

configuration option are:

• ASREQUIRED: Initial impedance calibration is made at device initialization, and

dynamic impedance adjustments are made as needed throughout device operation

(default).

• QUIET: Impedance calibration is done once at device initialization, or each time the RST

pin is asserted on the DCIRESET primitive for designs that include this primitive.

RECOMMENDED: It is strongly recommended that the DCIUpdateMode option be kept with the default

value of ASREQUIRED so that the DCI circuitry is allowed to operate normally.

DCIRESET Primitive

DCIRESET is an AMD design primitive that provides the capability to perform a reset of the

DCI controller state machine during normal operation of the design. This primitive is

required in a design when DCIUpdateMode is set to QUIET (see DCIUpdateMode

Configuration Option) or for the case outlined in Special DCI Requirements in Some Banks.

See the UltraScale Architecture Libraries Guide (UG974) [Ref 5] for more details on the

DCIRESET primitive.

Special DCI Requirements in Some Banks

When any of the multi-function pins in I/O bank 65 (or pins in bank 60 or bank 70 in devices

with multiple SLRs) are assigned as DCI I/O standards (in HP I/O bank devices), you should

also include and use the DCIRESET primitive in your design. In that case, the design should

pulse the RST input of DCIRESET and then wait for the LOCKED signal to be asserted prior

to using any of these pins’ inputs or outputs with DCI standards. This is required because

these I/O pins ignore the initial DCI calibration that happens during the normal device

initialization.

As a result, if the DCIRESET primitive had not been used and DCIUpdateMode was set to

ASREQUIRED, after those pins become normal I/O pins, there would be an indeterministic

delay between the end of configuration and when the DCI calibration algorithm updated

those pins’ DCI settings. If DCIRESET was not used and DCIUpdateMode was set to QUIET,

these pins would never have their DCI values set. Including and using the DCIRESET

primitive in the design allows these pins to have DCI I/O standards and to perform without

issue.

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Xilinx UltraScale架构SelectIO资源详解：v1.15用户指南

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