使用VHDL在FPGA上设计CPU教程

VHDL

CPU

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"设计自己的FPGA上的CPU使用VHDL" 这篇内容主要讲解了如何使用VHDL在FPGA（Field Programmable Gate Array，现场可编程门阵列）上设计一款自定义的CPU。作者是Dr. Juergen Sauermann，并提供了一些相关链接和工具的推荐。 1. **简介与概述** - **先决条件**: 在开始设计前，需要具备VHDL编程的基础知识以及对数字逻辑设计的理解。 - **其他有用链接**: 提供了其他有助于学习和理解FPGA和CPU设计的资源链接。 - **讲座结构**: 讲座分为多个部分，逐步深入介绍设计过程，包括顶级设计、CPU核心、指令获取、数据路径等关键环节。 2. **顶级设计** - **设计目的**: 顶级设计的目标是创建一个完整的CPU系统，它将包含CPU核心、内存和其他必要的外围设备接口。 - **顶级设计**: 这部分描述了如何在VHDL中构建CPU的顶层结构。 - **VHDL文件结构**: 通常包含头文件、库声明、实体声明和架构等内容。 3. **VHDL文件结构** - **头文件和库声明**: 定义使用的库和包，以便访问FPGA设计所需的特定功能。 - **实体声明**: 定义设计的外部接口，包括输入、输出和时钟信号。 - **实体架构**: 描述实体内部的工作原理，包括逻辑门和组合逻辑。 4. **avr_fpga.vhd**：这是顶级实体的VHDL代码，包含了前面提到的头文件、实体声明和架构，用于实现整个CPU的设计。 5. **组件树**：这部分详细描述了CPU设计中的各个组成部分，如内存模块、控制单元和数据路径组件等。 6. **旁路：流水线技术**：介绍了如何通过流水线技术来提高CPU的执行效率，使得指令处理可以在多个时钟周期内并行进行。 7. **CPU核心** - **指令获取**：这部分涵盖了程序存储器（Program Memory）的设计，包括使用双端口内存以支持读写操作，以及如何实现预取两个字的指令以减少延迟。 - **延迟PC（Program Counter）**：为了处理分支指令，需要有延迟PC来确保正确跳转到下一个指令地址。 - **两周期指令**：某些指令可能需要两个时钟周期来完成，这部分解释了如何处理这类指令。 - **中断**：介绍了CPU如何响应并处理中断请求，以中断当前执行流程。 8. **数据路径** - **寄存器文件**：数据路径中的重要组件，用于存储中间计算结果和通用目的寄存器。这个讲座深入浅出地介绍了FPGA上自定义CPU设计的各个方面，包括VHDL编程技巧、内存管理、指令获取机制和数据路径设计，对于想要了解或实践CPU设计的工程师非常有价值。

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2.4.3.1 Architecture Header

As we have seen in the first figure in this lesson, the top level uses 3 components: cpu, io, and seg. These

components have to be declared in the header of the architecture. The architecture contains component

declarations, signal declarations and others. We normally declare components and signals in the following

order:

declaration of functions•

declaration of constants•

declaration of the first component (type)•

declaration of signals driven by (an instance of) the first component•

declaration of the second component (type)•

declaration of signals driven by (an instance of) the second component•

...•

declaration of signals driven by local processes and the like.•

The first component declaration cpu_core and the signals driven by its instances are:

45 component cpu_core

46 port ( I_CLK : in std_logic;

47 I_CLR : in std_logic;

48 I_INTVEC : in std_logic_vector( 5 downto 0);

49 I_DIN : in std_logic_vector( 7 downto 0);

51 Q_OPC : out std_logic_vector(15 downto 0);

52 Q_PC : out std_logic_vector(15 downto 0);

53 Q_DOUT : out std_logic_vector( 7 downto 0);

54 Q_ADR_IO : out std_logic_vector( 7 downto 0);

55 Q_RD_IO : out std_logic;

56 Q_WE_IO : out std_logic);

57 end component;

59 signal C_PC : std_logic_vector(15 downto 0);

60 signal C_OPC : std_logic_vector(15 downto 0);

61 signal C_ADR_IO : std_logic_vector( 7 downto 0);

62 signal C_DOUT : std_logic_vector( 7 downto 0);

63 signal C_RD_IO : std_logic;

64 signal C_WE_IO : std_logic;

src/avr_fpga.vhd

The second component declaration io and its signals are:

66 component io

67 port ( I_CLK : in std_logic;

68 I_CLR : in std_logic;

69 I_ADR_IO : in std_logic_vector( 7 downto 0);

70 I_DIN : in std_logic_vector( 7 downto 0);

2 TOP LEVEL

71 I_RD_IO : in std_logic;

72 I_WE_IO : in std_logic;

73 I_SWITCH : in std_logic_vector( 7 downto 0);

74 I_RX : in std_logic;

76 Q_7_SEGMENT : out std_logic_vector( 6 downto 0);

77 Q_DOUT : out std_logic_vector( 7 downto 0);

78 Q_INTVEC : out std_logic_vector(5 downto 0);

79 Q_LEDS : out std_logic_vector( 1 downto 0);

80 Q_TX : out std_logic);

81 end component;

83 signal N_INTVEC : std_logic_vector( 5 downto 0);

84 signal N_DOUT : std_logic_vector( 7 downto 0);

85 signal N_TX : std_logic;

86 signal N_7_SEGMENT : std_logic_vector( 6 downto 0);

src/avr_fpga.vhd

Note: Normally we would have used I_ as a prefix for signals driven by instance ino of io. This conflicts,

however, with the prefix reserved for inputs and we have used the next letter n of ino as prefix instead.

The last component is seg:

88 component segment7

89 port ( I_CLK : in std_logic;

91 I_CLR : in std_logic;

92 I_OPC : in std_logic_vector(15 downto 0);

93 I_PC : in std_logic_vector(15 downto 0);

95 Q_7_SEGMENT : out std_logic_vector( 6 downto 0));

96 end component;

98 signal S_7_SEGMENT : std_logic_vector( 6 downto 0);

src/avr_fpga.vhd

The local signals, which are not driven by any component, but by local processes and inputs of the entity, are:

100 signal L_CLK : std_logic := '0';

101 signal L_CLK_CNT : std_logic_vector( 2 downto 0) := "000";

102 signal L_CLR : std_logic; -- reset, active low

103 signal L_CLR_N : std_logic := '0'; -- reset, active low

104 signal L_C1_N : std_logic := '0'; -- switch debounce, active low

105 signal L_C2_N : std_logic := '0'; -- switch debounce, active low

106

107 begin

2 TOP LEVEL

src/avr_fpga.vhd

The begin keyword in the last line marks the end of the header of the architecture and the start of its body.

2.4.3.2 Architecture Body

We normally use the following order in the architecture body:

components instantiated•

processes•

local signal assignments•

Thus the architecture body is more or less using the same order as the architecture header. The component

instantiations instantiate one or more instances of a component type and connect the "ports" of the instantiated

component to the signals in the architecture.

The first component declared was cpu so we also instantiate it first:

109 cpu : cpu_core

110 port map( I_CLK => L_CLK,

111 I_CLR => L_CLR,

112 I_DIN => N_DOUT,

113 I_INTVEC => N_INTVEC,

114

115 Q_ADR_IO => C_ADR_IO,

116 Q_DOUT => C_DOUT,

117 Q_OPC => C_OPC,

118 Q_PC => C_PC,

119 Q_RD_IO => C_RD_IO,

120 Q_WE_IO => C_WE_IO);

src/avr_fpga.vhd

The first line instantiates a component of type cpu_core and calls the instance cpu. The following lines map

the names of the ports in the component declaration (in the architecture header) to either inputs of the entity,

outputs of the entity, or signals declared in the architecture header.

We take cpu as an opportunity to explain our naming convention for signals. Our rule for entity inputs and

outputs has the consequence that all left sides of the port map have either an I_ prefix or an O_ prefix. This

follows from the fact that a component instantiated in one architecture corresponds to an entity declared in

some other VHDL file and there the I_ or O_ convention applies,

The next observation is that all component outputs either drive an entity output or a local signal that starts

with the letter chosen for the instantiated component. This is the C_ in the cpu case. The cpu does not drive

an entity output directly (so all outputs map to C_ signals), but in the io outputs there is one driving an entity

output (see below).

2 TOP LEVEL

Finally the component inputs can be driven from more or less anywhere, but from the prefix (L_ or not) we

can see if the signal is directly driven by another component (when the prefix is not L_) or by some logic

defined further down in the architecture (signal assignments, processes).

Thus for the cpu component we can already tell that this component drives a number of local signals (that are

not entity outputs but inputs to other components or local processes)> These signals are those on the right side

of the port map starting with C_. We can also tell that there are some local processes generating a clock signal

L_CLK and a reset signal L_CLR, and the ino component (which uses prefix N_) drives an interrupt vector

N_INTVEC and a data bus N_DOUT.

The next two components being instantiated are ino of type io and seg of type segment7:

122 ino : io

123 port map( I_CLK => L_CLK,

124 I_CLR => L_CLR,

125 I_ADR_IO => C_ADR_IO,

126 I_DIN => C_DOUT,

127 I_RD_IO => C_RD_IO,

128 I_RX => I_RX,

129 I_SWITCH => I_SWITCH(7 downto 0),

130 I_WE_IO => C_WE_IO,

131

132 Q_7_SEGMENT => N_7_SEGMENT,

133 Q_DOUT => N_DOUT,

134 Q_INTVEC => N_INTVEC,

135 Q_LEDS => Q_LEDS(1 downto 0),

136 Q_TX => N_TX);

137

138 seg : segment7

139 port map( I_CLK => L_CLK,

140 I_CLR => L_CLR,

141 I_OPC => C_OPC,

142 I_PC => C_PC,

143

144 Q_7_SEGMENT => S_7_SEGMENT);

src/avr_fpga.vhd

Then come the local processes. The first process divides the 100 MHz input clock from the board into a 25

MHz clock used by the CPU. The design can, with some tuning of the timing optimizations, run at 33 MHz,

but for our purposes we are happy with 25 MHz.

148 clk_div : process(I_CLK_100)

149 begin

150 if (rising_edge(I_CLK_100)) then

151 L_CLK_CNT <= L_CLK_CNT + "001";

152 if (L_CLK_CNT = "001") then

153 L_CLK_CNT <= "000";

154 L_CLK <= not L_CLK;

2 TOP LEVEL

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