DDR3L SDRAM手册：低电压版DDR3技术规格

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"DDR3L手册提供了关于DDR3低电压版本SDRAM的详细技术规格，包括不同内存容量的芯片型号，如MT41K2G4、MT41K1G8和MT41K512M16。手册强调了DDR3L在1.35V工作模式下的特点，同时也支持向后兼容1.5V的DDR3设备。内容涵盖数据 strobe、8n位预取架构、差分时钟输入、8个内部银行、各种可编程延迟参数、固定及动态的突发长度控制、自我刷新模式以及温度相关的刷新机制等。" DDR3L SDRAM是DDR3内存标准的一个低电压变体，设计工作电压为1.35V（具体范围为1.283V到1.45V），旨在降低功耗，适用于对能耗有严格要求的系统。它同时具有与标准DDR3设备的向后兼容性，这意味着DDR3L设备可以在支持1.5V电压的系统中正常工作。该手册详细介绍了DDR3L内存的关键特性。首先，内存使用差分双向数据 strobe，确保数据传输的稳定性和速度。8n位预取架构提高了数据处理效率，使得内存能更快地处理数据包。此外，内存模块采用差分时钟输入（CK和CK#），以减少信号干扰并提高时钟精度。 DDR3L内存具有8个内部银行，这增强了并发访问能力，提高了多任务环境下的性能。手册还提到，数据、strobes和mask信号都支持名义上和动态的片选线（ODT），可以根据系统需求进行配置。其他关键参数如CAS（读取）延迟（CL）、附加CAS延迟（AL）、CAS（写入）延迟（CWL）以及突发长度（BL）和突发切分（BC）都可以通过程序进行设置，以优化内存性能。自我刷新模式（Self refresh mode）和自动自我刷新（ASR）是DDR3L内存的重要节能特性，能在系统待机或低功耗状态下保持数据完整性。手册还规定了不同温度下不同的刷新周期，以确保数据在各种环境条件下的稳定性。特别地，提供了针对高温环境的自我刷新温度（SRT）功能，以适应宽温范围的操作。写级别调整（Write leveling）确保了数据写入时的精确时序，而多功能寄存器则允许用户自定义和控制各种内存操作参数。最后，输出驱动校准确保了数据传输的质量和一致性。 DDR3L手册是深入理解DDR3L内存规格和技术细节的重要参考资料，对于硬件设计师、系统集成商和内存优化专家来说，它是不可或缺的技术文档。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A15

A12/BC#

A11

A14

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. D 8/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Com-

mand section.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ุ 0.8 × V

and

DC LOW ื 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. D 8/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See the Truth Table – Com-

mand section.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle),or active power-down (row active in any bank). CKE is synchronous for power-

down entry and exit and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during

POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF

REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# pro-

vides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a

write access. Although the LDM ball is input-only, the LDM loading is

designed to match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,

LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,

and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for

the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is

referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

8Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. D 8/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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