Micron DDR3L 芯片手册：1.35V低电压设计与特性

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"DDR3L 芯片手册是针对Micron公司的2Gb DDR3L参考设计，涉及的芯片型号包括MT41K128M16XXX和MT41K256M8XXX等。手册详细介绍了1.35V DDR3L SDRAM设备的特性和功能，如低电压操作、双向差分数据 strobe、8n位预取架构等，并提供了多种可编程参数，如CAS延迟、突发长度等。此外，还包括自刷新模式、温度控制和输出驱动校准等功能。" DDR3L SDRAM是DDR3内存标准的一个低电压版本，旨在降低功耗，提高能效。MT41K系列芯片提供了不同容量的选择，例如MT41K512M4、MT41K256M8和MT41K128M16，分别对应512兆字节（Megabit）x4、256兆字节x8和128兆字节x16的配置，它们都有8个内部银行，这使得数据访问更为高效。在电压方面，DDR3L的工作电压VDD和VDDQ被设定为1.35V，允许的范围是1.283V到1.45V，这比标准的1.5V DDR3降低了近15%。此外，它还兼容1.5V的工作模式，这意味着在不支持1.35V的系统中，这些芯片仍可以正常工作。该技术采用了差分双向数据 strobe，确保数据传输的稳定性和准确性。8n位预取架构则意味着数据总线宽度为8倍的内存单元宽度，提高了数据传输速率。同时，DDR3L SDRAM具有差分时钟输入（CK和CK#），确保时钟信号的清晰和抗干扰能力。 DDR3L SDRAM的其他特性包括可编程的CAS（读取）延迟（CL）、可编程的POST CAS附加延迟（AL）、可编程的CAS（写入）延迟（CWL），以及固定的8位突发长度（BL）和4位突发切分（BC）。通过模式寄存器集（MRS），用户可以根据需求调整这些参数，实现灵活的数据访问控制。自刷新模式允许芯片在低功耗状态下维持数据完整性，特别适合移动设备和节能应用。此外，还有温度控制的自刷新（TC of 95°C）功能，根据环境温度调整刷新周期，确保数据的可靠性。自动自刷新（ASR）进一步简化了系统管理，而写入均衡和多用途寄存器则优化了信号质量。 DDR3L SDRAM芯片在保持高性能的同时，通过低电压操作和各种优化特性实现了能效的提升，是现代电子设备特别是移动设备的理想选择。对于开发者和硬件工程师来说，这份手册提供了全面的技术细节，有助于他们设计和集成这些内存芯片到他们的系统中。

Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 512 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

Address

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To pullup/pulldown

networks

READ

drivers

DQ[3:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

CK,CK#

DQS, DQS#

ODT

control

ZQ CAL

WE#

RZQ

CK, CK#

RAS#

CAS#

CS#

ODT

CKE

RESET#

CK,CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

DDQ

TT,nom

TT(WR)

BC4

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

A12

SSQ

OTF

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 4: 256 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(32,768 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read

drivers

DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

SW1 SW2

DDQ

TT(WR)

TT,nom

SW1 SW2

DDQ

TT,nom

TT(WR)

SW1 SW2

DDQ

TT,nom

TT(WR)

BC4 (burst chop)

BC4

Write

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

Address

A12

SSQ

OTF

Figure 5: 128 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

SW1

SW2

DDQ

BC4

SW1

SW2

DDQ

TT,nom

TT(WR)

SW1

SW2

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

DDQ

TT,nom

TT(WR)

TT,nom

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

DDQ

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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