Micron DDR3L 1.35V SDRAM规格与特性详解

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"Micron DDR3用户手册详细介绍了1.35V低电压DDR3 SDRAM设备，包括不同型号如MT41K256M4、MT41K128M8和MT41K64M16的规格和特性。该手册涵盖了DDR3 SDRAM的主要功能，如双差分数据 strobe、8n位预取架构、内部8个银行、以及多种可编程延迟设置等。此外，手册还提到了自我刷新模式、温度范围、自我刷新温度控制（SRT）、自动自我刷新（ASR）等功能，以及输出驱动校准等选项。" DDR3 SDRAM是内存技术的一个重要里程碑，它在DDR2的基础上进行了优化，提供了更高的数据传输速率和更低的功耗。Micron的1.35V DDR3L（Low Voltage）系列内存芯片是在1.5V DDR3基础上的节能版本，旨在减少工作电流，从而降低整体系统功耗。 MT41K256M4、MT41K128M8和MT41K64M16是不同容量的DDR3 SDRAM芯片，分别表示256兆字节（Megabit）x4位、128兆字节x8位和64兆字节x16位的配置。这些芯片具有8个内部银行，可以并行处理多个数据请求，提高了内存访问效率。此外，DDR3内存采用差分双向数据 strobe，确保了数据传输的准确性和稳定性。该手册中的关键特性包括： 1. **电压兼容性**：VDD和VDDQ引脚工作在1.35V（1.283V到1.45V），并向下兼容1.5V标准。 2. **8n位预取架构**：提高数据吞吐量，使得每个时钟周期可以处理更多数据。 3. **可编程CAS延迟**：包括读取（CL）、附加（AL）和写入（CWL）延迟，允许根据系统需求进行微调。 4. **固定突发长度**：默认为8，并通过模式寄存器集（MRS）支持4的突发切片（Burst Chop）。 5. **自适应刷新**：提供64ms和32ms两种刷新模式，以适应不同的温度条件。 6. **自我刷新技术**：包括标准的自我刷新模式、自适应刷新（ASR）和自我刷新温度控制（SRT），确保在不同环境温度下的稳定工作。 7. **写入校准**和**输出驱动校准**：保证数据传输的精确性和一致性。这些特性使Micron DDR3 SDRAM适用于对速度、功耗和可靠性有高要求的应用，如高性能计算、服务器和工作站等。用户手册详细阐述了如何配置和优化这些功能，以适应各种系统设计需求。

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)

1234 67895

DDQ

SSQ

REFDQ

ODT

SSQ

DQ2

NF, DQ6

DDQ

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

NF, DQ7

CK#

A10/AP

A12/BC#

A11

DDQ

SSQ

DDQ

CKE

SSQ

DQ3

NF, DQ5

REFCA

BA1

Notes:

1. Ball descriptions listed in Table 3 (page 18) are listed as x4, x8 if unique; otherwise, x4

and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

1Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef833b7221

1Gb_DDR3L.pdf - Rev. K EN 9/14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[9:0], A10/AP,

A11, A12/BC#,

A13

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to V

REFCA

. A12/BC#: when enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop).

BA[2:0] Input Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to V

REFDQ

. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and DC LOW ≤

0.2 × V

DDQ

. RESET# assertion and de-assertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to V

REFDQ

1Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef833b7221

1Gb_DDR3L.pdf - Rev. K EN 9/14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A[9:0], A10/AP,

A11, A12/BC#

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one loca-

tion out of the memory array in the respective bank. A10 sampled during a PRE-

CHARGE command determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-

vide the op-code during a LOAD MODE command. Address inputs are referenced to

REFCA

. A12/BC#: when enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,

or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,

MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are refer-

enced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-

pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle) or

active power-down (row active in any bank). CKE is synchronous for power-down en-

try and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input

buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down.

Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is

referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com-

mand decoder. All commands are masked when CS# is registered HIGH. CS# provides

for external rank selection on systems with multiple ranks. CS# is considered part of

the command code. CS# is referenced to V

REFCA

LDM Input Input data mask: LDM is a lower byte, input mask signal for write data. Lower-byte

input data is masked when LDM is sampled HIGH along with the input data during a

write access. Although the LDM ball is input-only, the LDM loading is designed to

match that of the DQ and DQS balls. LDM is referenced to V

REFDQ

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal opera-

tion, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,

UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/

TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4.

The ODT input is ignored if disabled via the LOAD MODE command. ODT is

referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command be-

ing entered and are referenced to V

REFCA

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and DC

LOW ≤ 0.2 × V

DDQ

. RESET# assertion and de-assertion are asynchronous.

1Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

PDF: 09005aef833b7221

1Gb_DDR3L.pdf - Rev. K EN 9/14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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