Intel Xeon处理器E7家族的RAS特性解析

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"英特尔至强处理器E7家族的RAS特性是针对关键任务部署的高级数据完整性和恢复支持，旨在提高服务器的可靠性、可用性和服务性。这些特性包括错误检测、纠正、遏制和恢复功能，涵盖了处理器、内存和I/O数据路径。这为硬件和软件供应商提供了构建更高级RAS层的基础，以实现整体服务器的高可靠性。" Intel Xeon RAS（可靠性、可用性和服务性）是Intel Xeon处理器系列中的一项关键功能，特别在Intel Xeon Processor E7家族中得到了强化。RAS是企业级IT环境中的重要因素，因为这些环境通常运行着对数据敏感且至关重要的应用程序。当服务器的RAS性能不足时，系统停机可能造成高昂的成本，每小时的故障损失都可能非常巨大。随着现代企业的数据量和服务器规模的增长，故障发生的概率也随之增加。因此，Intel Xeon Processor E7家族通过提供一套全面且强大的硅基RAS特性来应对这一挑战。这些特性包括： 1. **高级数据完整性**：确保数据在处理、存储和传输过程中的准确性，通过校验和、纠错编码等技术检测并修复数据错误。 2. **错误检测与纠正**：内置的ECC（错误校正码）内存可以检测和纠正单个比特错误，甚至在某些情况下可以检测到并修复多比特错误，保护内存免受数据损坏。 3. **错误遏制**：当发生错误时，RAS特性能够限制错误的影响范围，防止错误扩散到整个系统。 4. **恢复机制**：快速的故障切换和恢复策略确保系统能在故障发生后迅速恢复正常运行，减少停机时间。 5. **I/O数据路径保护**：RAS不仅关注处理器和内存，还涵盖输入输出（I/O）系统，确保数据在传输过程中不受干扰。 6. **硬件级支持**：Intel Xeon处理器E7家族的硬件设计包含专门的RAS功能，如硬件故障指示器和自恢复机制，为上层软件提供稳定的基础。 7. **软件协作**：RAS特性也鼓励与操作系统、虚拟化软件和其他管理程序的紧密集成，以提供端到端的解决方案，增强整个系统的稳定性。 8. **热插拔和冗余组件**：支持热插拔硬盘、电源模块和风扇，允许在不中断系统运行的情况下进行维护或更换故障部件。 9. **智能自诊断**：通过内置的监控和诊断工具，系统能够预测并预防潜在的硬件问题，提前采取措施避免故障发生。通过这些综合性的RAS特性，Intel Xeon Processor E7家族不仅提升了服务器的正常运行时间，还降低了故障恢复的时间和成本。这使得基于Intel Xeon的服务器成为运行关键业务应用的理想选择，特别是在金融、医疗、电信和大数据分析等领域，对系统连续性和数据安全性有着极高要求的场景。

A STUDY OF MEMORY ERRORS

Google® Inc. researchers conducted a

two-year study of memory errors in

Google‟s server fleet (see Google Inc.,

“DRAM Errors in the Wild: A Large-Scale

Field Study,” in the References section).

All of the servers in the study were

protected by ECC, in the form of either

SECDED or Chipkill. Researchers found

that ECC fixed most of the memory

errors. In that study, Chipkill technology

was more effective in correcting errors

by a factor of 4 to 10 over the less-

powerful SECDED codes.

Researchers observed more than

8 percent of DIMMS and about

one-third of the machines in the

study were affected by

correctable (DCE) errors per year.

Researchers observed more than 8

percent of DIMMS and about one-third of

the machines in the study were affected

by correctable (DCE) errors per year, and

DIMMs averaged nearly 4,000

correctable errors per year. The study

found FIT rates (failures in time per

billion device hours) of 25,000 to 70,000

per Mbit. The annual percentage of

detected, uncorrected errors (DUE) was

1.3 percent per machine and 0.22

percent per DIMM.

DCEs can be handled by ECC and

therefore are largely transparent to the

running application. As the Google paper

concludes, the DUE rate makes a crash-

tolerant layer indispensable for large-

scale server farms.

The Google research studied whether

errors could be used to detect future

errors. It found that DCEs in DIMMs

provide a strong indication of future

DCEs and DUEs. For the analysis, the

researchers sorted the servers into six

platform groups, defined by motherboard

and memory generation. For each tested

platform, they found that in 85 percent

of cases, a DCE was followed by at least

one more DCE in the same month, making

the various platforms from 13 to 90

times more likely to have DCEs later in

the month compared to an average

month. DCEs in the previous month also

increased the probability of DCEs. DUEs

were 27 to 400 times more likely in a

month with DCEs, and from 9 to 47 times

more likely if there had been DCEs the

previous month.

The research also found similar, though

much slighter, correlations among

failures in DIMMs in the same system,

with systems that experienced failures

on any DIMMs more likely to soon have

failures on other DIMMs.

The Google researchers analyzed

external factors related to errors. They

found that memory utilization and age of

DIMMs strongly correlated with memory

errors. Correctable error rates increased

almost logarithmically as a function of

utilization levels. The incidence of

For each tested platform, they

found that in 85 percent of

cases, a DCE was followed by at

least one more DCE in the same

month,

correctable errors increased with DIMM

age, while the incidence of uncorrectable

errors decreased with age (due to

replacements of DIMMs with those

errors). DIMM capacity and operating

temperature, two factors previously

thought to affect errors, did not correlate

with error. The study found no evidence

of worse error behavior among newer

generation, higher-capacity DIMMs.

Within the range of temperatures of the

tested production systems, temperature

also did not correlate with errors.

Intel Xeon Processor E7 Family: Reliability, Availability, and Serviceability

More advanced ECC technologies can

increase reliability. These include

IBM® Chipkill™ technology, which can

correct and detect more error bits in

a single memory word than

traditional ECCs. Chipkill can correct

up to eight adjacent error bits, and

thus can correct a broken four or

eight-bit-wide DRAM chip. Chipkill is

frequently combined with sparing, so

that if a memory chip fails (or

exceeds a threshold of correctable

bit errors), a spare memory chip is

used to replace it. Chipkill technology

lets servers withstand errors that

could crash a system with less

advanced error correction. Although

IBM introduced the technology, today

other vendors have equivalent

technologies. Sun Microsystems, now

a subsidiary of Oracle Corporation,

calls its approach Extended ECC, and

HP calls its approach Chipspare. Intel

introduced Single Device Data

Correction (SDDC), in the 1990‟s

which uses ECC to protect against

single x4 or x8 DRAM device failure.

Intel also provides a more advanced

memory correction technology called

Enhanced Double Device Data

Correction (DDDC), which allows

recovery from two sequential DRAM

failures on the memory DIMMs, as

well as recovery from a subsequent

single-bit soft error on the DIMM.

ADVANCED RAS AND THE INTEL

XEON PROCESSOR E7 FAMILY

The Intel Xeon Processor E7

Family

The Intel Xeon processor E7 family

delivers top-of-the-line performance

for the most data-demanding

workloads and mission-critical

applications. Built on the 32 nm Intel

process technology, the Intel Xeon

processor E7 family offers an

increased core count of up to 10

cores and 20 hardware threads in

either four- or eight-socket

configurations. For massive

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