Cypress S25FL128S/S25FL256S SPI Flash Memory Chip Manual

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"S25FL128S是一款由 Cypress Semiconductor Corporation 生产的SPI闪存芯片，主要用于存储数据。该芯片提供128兆比特（16兆字节）的存储容量，采用3.0伏的核心CMOS技术，并且支持SPI多I/O接口。手册详细介绍了其特性、读写操作、编程与擦除功能以及错误校验等高级功能。" S25FL128S是Cypress Semiconductor推出的一款高密度SPI闪存芯片，主要用于需要高速、低功耗存储解决方案的应用场景。这款芯片的主要特点包括： 1. **电压兼容性**：它采用3.0伏的CMOS核心，能够适应各种工作环境，同时保持高效能和低功耗。 2. **SPI接口与多I/O支持**：S25FL128S支持SPI接口，且提供了SPI多I/O模式，包括SPI时钟极性和相位模式0和3，以及双输入、四输入模式，允许更快速的数据传输。此外，还有DDR（Double Data Rate）选项，进一步提高数据读取速率。 3. **地址扩展**：支持24位和32位的地址选项，使得在大容量存储中可以访问到更广阔的地址空间。 4. **兼容性**：该芯片的串行命令集和脚印与S25FL-A、S25FL-K和S25FL-PS系列SPI家族兼容，而多I/O命令集则与S25FL-PSPI家族兼容，方便在不同设计中进行替换或升级。 5. **读取命令**：提供多种读取方式，如正常读、快速读、双I/O读、四I/O读、快速DDR、双I/O DDR和四I/O DDR，满足不同速度需求。其中，自动启动功能可在电源上电或复位后自动执行预设的读取命令。 6. **编程功能**：具备256字节或512字节的页编程缓冲区，支持慢速时钟系统的四输入页编程（QPP）。内置ECC（错误校验码）硬件，能进行单比特错误修正，确保数据的可靠性。 7. **擦除功能**：采用混合扇区设计，每个物理扇区包含32个4KB的小扇区，擦除速度在0.5至0.65MBps之间，提供灵活的擦除操作。 8. **配置信息**：支持Common Flash Interface (CFI) 数据，用于获取配置信息，简化了设备的初始化和管理。 9. **安全性**：除了自动ECC功能，S25FL128S可能还提供了其他的安全特性，例如保护区域、安全擦除或写锁定，以保护存储在其中的数据免受未授权访问。 S25FL128S是一款高性能、高容量的SPI闪存，适用于嵌入式系统、物联网设备、工业控制和消费电子等多种应用场景，它的多种读写模式和扩展功能使其在数据存储领域具有广泛的应用前景。

Document Number: 001-98283 Rev. *P Page 16 of 145

S25FL128S/S25FL256S

Figure 12. Dual Output Command

Figure 13. Quad Output Command without Latency

Figure 14. Dual I/O Command

Figure 15. Quad I/O Command

Figure 16. DDR Fast Read with EHPLC = 00b

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1

Instruction Address 6 Dummy Data 1 Data 2

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

Instruction Address Data 1 Data 2 Data 3 Data 4 Data 5 ...

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0

31 3 1 7 5 3 1 7 5 3 1

Instruction Address Dummy Data 1 Data 2

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 28 4 0 4 4 0 4 0 4 0 4 0

29 5 1 5 5 1 5 1 5 1 5 1

30 6 2 6 6 2 6 2 6 2 6 2

31 7 3 7 7 3 7 3 7 3 7 3

Instruction Address Mode Dummy D1 D2 D3 D4

CS#

SCK

Phase

7 6 5 4 3 2 1 0 3130 0 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Instruction Address Mode Dummy Data 1 Data 2

Document Number: 001-98283 Rev. *P Page 17 of 145

S25FL128S/S25FL256S

Figure 17. DDR Dual I/O Read with EHPLC = 01b and DLP

Figure 18. DDR Quad I/O Read

Additional sequence diagrams, specific to each command, are provided in Section 9. Commands on page 63.

3.3 Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

Table 3. Interface States Summary

Interface State V

RESET

SCK CS#

HOLD#

/ IO3

WP# /

IO2

SO / IO1 SI / IO0

Power-Off < V

(low)  V

XXXXXZX

Low Power

Hardware Data Protection

(cut-off)  V

XXXXXZX

Power-On (Cold) Reset ≥ V

(min) ≥ V

(min) ≤ V

XXXXXZX

Hardware (Warm) Reset ≥ V

(min) ≥ V

(min) ≤ V

HL X X X X Z X

Interface Standby ≥ V

(min) ≥ V

(min) ≤ V

HH X HH X X Z X

Instruction Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HT HL HH HV Z HV

Hold Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HV or HT HL HL X X X

Single Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL HH X Z HV

Single Latency (Dummy) Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HT HL HH X Z X

Single Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL HH X MV X

Dual Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL HH X HV HV

Dual Latency (Dummy) Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HT HL HH X X X

Dual Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL HH X MV MV

QPP Address Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL X X X HV

Quad Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL HV HV HV HV

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 30 28 0 6 4 2 0 7 6 5 4 3 2 1 0 6 4 2 0 6

31 29 1 7 5 3 1 7 6 5 4 3 2 1 0 7 5 3 1 7

Instruction Address Mode Dum DLP Data 1

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 28 242016 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0

2925 211713 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1

3026 221814 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2

3127 231915 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3

Instruction Address

Mode

Dummy DLP D1 D2

Document Number: 001-98283 Rev. *P Page 18 of 145

S25FL128S/S25FL256S

Legend

Z = No driver - floating signal

HL = Host driving V

HH = Host driving V

HV = Either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V

MH = Memory driving V

MV = Either ML or MH

3.3.1 Power-Off

When the core supply voltage is at or below the V

(low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation.

3.3.2 Low Power Hardware Data Protection

When V

is less than V

(cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.3.3 Power-On (Cold) Reset

When the core voltage supply remains at or below the V

(low) voltage for  t

time, then rises to  V

CC (Minimum)

the device will

begin its Power-On Reset (POR) process. POR continues until the end of t

. During t

, the device does not react to external input

signals nor drive any outputs. Following the end of t

, the device transitions to the Interface Standby state and can accept

commands. For additional information on POR, see Section 5.3.1 Power-On (Cold) Reset on page 29.

3.3.4 Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven LOW for t

time, the device starts the

hardware reset process. The process continues for t

RPH

time. Following the end of both t

RPH

and the reset hold time following the

rise of RESET# (t

) the device transitions to the Interface Standby state and can accept commands. For additional information on

hardware reset, see Section 28 POR followed by Hardware Reset on page 29.

Quad Latency (Dummy) Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HT HL X X X X

Quad Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL MV MV MV MV

DDR Single Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL X X X HV

DDR Dual Input Cycle

Host to Memory Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL X X HV HV

DDR Quad Input Cycle

Host to Memory Transfer

≥V

(min)

≥V

(min)

≤V

HH HT HL HV HV HV HV

DDR Latency (Dummy) Cycle ≥ V

(min) ≥ V

(min) ≤ V

HH HT HL MV or Z MV or Z MV or Z MV or Z

DDR Single Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL Z Z MV X

DDR Dual Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL Z Z MV MV

DDR Quad Output Cycle

Memory to Host Transfer

≥V

(min) ≥ V

(min) ≤ V

HH HT HL MV MV MV MV

Table 3. Interface States Summary (Continued)

Interface State V

RESET

SCK CS#

HOLD#

/ IO3

WP# /

IO2

SO / IO1 SI / IO0

Document Number: 001-98283 Rev. *P Page 19 of 145

S25FL128S/S25FL256S

3.3.5 Interface Standby

When CS# is HIGH, the SPI interface is in Standby state. Inputs other than RESET# are ignored. The interface waits for the

beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a new command.

While in interface Standby state, the memory device draws standby current (I

) if no embedded algorithm is in progress. If an

embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to

standby current draw.

3.3.6 Instruction Cycle

When the host drives the MSb of an instruction and CS# goes LOW, on the next rising edge of SCK the device captures the MSb of

the instruction that begins the new command. On each following rising edge of SCK, the device captures the next lower significance

bit of the 8-bit instruction. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives Write Protect (WP#) signal as

needed for the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.

The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.

The expected next interface state depends on the instruction received.

Some commands are standalone, needing no address or data transfer to or from the memory. The host returns CS# HIGH after the

rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.7 Hold

When Quad mode is not enabled (CR[1]=0), the HOLD# / IO3 signal is used as the HOLD# input. The host keeps RESET# HIGH,

HOLD# LOW, SCK may be at a valid level or continue toggling, and CS# is LOW. When HOLD# is LOW a command is paused, as

though SCK were held LOW. SI / IO0 and SO / IO1 ignore the input level when acting as inputs and are high impedance when acting

as outputs during Hold state. Whether these signals are input or output depends on the command and the point in the command

sequence when HOLD# is asserted LOW.

When HOLD# returns HIGH, the next state is the same state the interface was in just before HOLD# was asserted LOW.

When Quad mode is enabled, the HOLD# / IO3 signal is used as IO3.

During DDR commands, the HOLD# and WP# inputs are ignored.

3.3.8 Single Input Cycle - Host to Memory Transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The

dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The

host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives SI as needed for the command. The memory does not drive the

Serial Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory

using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.

3.3.9 Single Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During

the latency cycles, the host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The

host may drive the SI signal during these cycles or the host may leave SI floating. The memory does not use any data driven on SI /

I/O0 or other I/O signals during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the

falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (SO) or I/

O signals during the latency cycles.

The next interface state depends on the command structure i.e., the number of latency cycles, and whether the read is single, dual,

or quad width.

Document Number: 001-98283 Rev. *P Page 20 of 145

S25FL128S/S25FL256S

3.3.10 Single Output Cycle - Memory to Host Transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps RESET# HIGH,

CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal. The

memory drives SO with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to HIGH ending the command.

3.3.11 Dual Input Cycle - Host to Memory Transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps RESET# HIGH, CS#

LOW, HOLD# HIGH. The Write Protect (WP#) signal is ignored. The host drives address on SI / IO0 and SO / IO1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency cycles needed or

Dual Output Cycle if no latency is required.

3.3.12 Dual Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the Configuration Register (CR[7:6]).

During the latency cycles, the host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored.

The host may drive the SI / IO0 and SO / IO1 signals during these cycles or the host may leave SI / IO0 and SO / IO1 floating. The

memory does not use any data driven on SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and

SO / IO1 on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency

cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency

cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the

SI / IO0 and SO / IO1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

3.3.13 Dual Output Cycle - Memory to Host Transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET# HIGH, CS# LOW,

and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / IO0 and SO / IO1 signals during

the dual output cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to HIGH ending the command.

3.3.14 QPP or QOR Address Input Cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0. The other IO signals are

ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active. The

host keeps RESET# HIGH, CS# LOW, and drives IO0.

For QPP the next interface state following the delivery of address is the Quad Input Cycle.

For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or Quad Output

Cycle if no latency is required.

3.3.15 Quad Input Cycle - Host to Memory Transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page Program command

transfers four data bits to the memory in each cycle. The host keeps RESET# HIGH, CS# LOW, and drives the IO signals.

For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are

latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host returns CS# HIGH following

the delivery of data to be programmed and the interface returns to standby state.

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