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Document Number: 001-98283 Rev. *P Page 19 of 145
3.3.5 Interface Standby
When CS# is HIGH, the SPI interface is in Standby state. Inputs other than RESET# are ignored. The interface waits for the
beginning of a new command. The next interface state is Instruction Cycle when CS# goes LOW to begin a new command.
While in interface Standby state, the memory device draws standby current (I
SB
) if no embedded algorithm is in progress. If an
embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to
standby current draw.
3.3.6 Instruction Cycle
When the host drives the MSb of an instruction and CS# goes LOW, on the next rising edge of SCK the device captures the MSb of
the instruction that begins the new command. On each following rising edge of SCK, the device captures the next lower significance
bit of the 8-bit instruction. The host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives Write Protect (WP#) signal as
needed for the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.
Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.
The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.
The expected next interface state depends on the instruction received.
Some commands are standalone, needing no address or data transfer to or from the memory. The host returns CS# HIGH after the
rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.
3.3.7 Hold
When Quad mode is not enabled (CR[1]=0), the HOLD# / IO3 signal is used as the HOLD# input. The host keeps RESET# HIGH,
HOLD# LOW, SCK may be at a valid level or continue toggling, and CS# is LOW. When HOLD# is LOW a command is paused, as
though SCK were held LOW. SI / IO0 and SO / IO1 ignore the input level when acting as inputs and are high impedance when acting
as outputs during Hold state. Whether these signals are input or output depends on the command and the point in the command
sequence when HOLD# is asserted LOW.
When HOLD# returns HIGH, the next state is the same state the interface was in just before HOLD# was asserted LOW.
When Quad mode is enabled, the HOLD# / IO3 signal is used as IO3.
During DDR commands, the HOLD# and WP# inputs are ignored.
3.3.8 Single Input Cycle - Host to Memory Transfer
Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The
dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The
host keeps RESET# HIGH, CS# LOW, HOLD# HIGH, and drives SI as needed for the command. The memory does not drive the
Serial Output (SO) signal.
The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory
using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.
3.3.9 Single Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before
transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During
the latency cycles, the host keeps RESET# HIGH, CS# LOW, and HOLD# HIGH. The Write Protect (WP#) signal is ignored. The
host may drive the SI signal during these cycles or the host may leave SI floating. The memory does not use any data driven on SI /
I/O0 or other I/O signals during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the
falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that
there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents
driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (SO) or I/
O signals during the latency cycles.
The next interface state depends on the command structure i.e., the number of latency cycles, and whether the read is single, dual,
or quad width.