Cypress S25FL512S 3.0V SPI Flash Memory 数据手册

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"S25FL512SAGMFI011.pdf 是 Cypress Semiconductor Corporation 生产的一款串行 NOR Flash 存储器的数据手册。这款芯片具有3.0V的CMOS核心电压，并且支持多I/O的串行外围接口（SPI）。其主要特点包括512Mbit（64Mbyte）的存储容量、SPI接口的各种工作模式（如SPI时钟极性和相位模式0和3，以及双数据速率选项），以及与S25FL-A、S25FL-K和S25FL-PSPI系列兼容的命令集和引脚布局。此外，它还具备多种读取命令，如正常读、快速读、双I/O、四I/O、快速DDR、双I/O DDR和四I/O DDR，以及自动启动功能。在编程方面，S25FL512S有512字节的页面编程缓冲区，支持慢速时钟系统的四输入页面编程（QPP）和内部硬件ECC，能进行单比特错误校正。擦除操作可在0.5到0.25秒之间完成，具有较高的效率。" 这篇文档详细介绍了S25FL512S串行NOR Flash存储器的技术规格和特性。NOR Flash是一种非易失性存储技术，数据在断电后仍能保持，常用于微控制器、嵌入式系统和某些类型的固件存储。这款芯片的3.0V CMOS核心电压使其适合低功耗应用。SPI接口是一种简单而高效的串行通信协议，支持多种操作模式，使其在不同类型的系统中具有良好的兼容性。 512Mbit的存储容量相当于64MB，足够存储大量的程序代码或配置数据。SPI接口的灵活性使得它可以适应不同的系统需求，如SPIClock polarity and phase modes 0 and 3允许用户根据系统时序来调整接口设置。双数据速率（DDR）选项则可以在相同时间内传输更多的数据，提高数据传输速度。该芯片还提供了一种称为AutoBoot的功能，可以在电源开启或复位时自动执行预设地址的正常读或四I/O读取命令，这对于系统的快速启动和自检过程非常有用。同时，CFI（Common Flash Interface）数据提供了配置信息，帮助系统识别和配置Flash存储器。在编程功能上，S25FL512S有一个512字节的页面编程缓冲区，可以实现快速的编程操作。四输入页面编程（QPP）对于那些使用较低频率时钟的系统来说，是提升编程效率的一个选项。内置的ECC（Error Correction Code）硬件能检测并纠正单比特错误，增加了数据的可靠性。最后，芯片的擦除操作速度快，范围在0.5到0.25秒之间，这在需要频繁擦写操作的应用中是一个重要的优点。S25FL512S是一款高性能、高可靠性的串行NOR Flash存储解决方案，适用于各种需要快速数据访问和稳定存储的应用场景。

Document Number: 001-98284 Rev. *M Page 16 of 134

S25FL512S

 At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after

the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be

driven high when the number of clock cycles after CS# signal was driven low is an exact multiple of eight cycles. If the CS#

signal does not go high exactly at the eight SCK cycle boundary of the instruction or write data, the command is rejected

and not executed.

 All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The data bits are

shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address byte sent first.

Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.

 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored.

The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during

an embedded operation. These are discussed in the individual command descriptions.

 Depending on the command, the time for execution varies. A command to read status information from an executing

command is available to determine when the command completes execution and whether the command was successful.

3.2.1 Command Sequence Examples

Figure 7. Stand Alone Instruction Command

Figure 8. Single Bit Wide Input Command

Figure 9. Single Bit Wide Output Command

Figure 10. Single Bit Wide I/O Command without Latency

CS#

SCK

Phase

76543210

Instruction

CS#

SCK

Phase

7654321076543210

Instruction Input Data

CS#

SCK

Phase

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Instruction Data 1 Data 2

CS#

SCK

Phase

7 6 5 4 3 2 1 0 31 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Instruction Address Data 1 Data 2

Document Number: 001-98284 Rev. *M Page 19 of 134

S25FL512S

Legend:

Z = no driver - floating signal

HL = Host driving V

HH = Host driving V

HV = either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V

MH = Memory driving V

MV = either ML or MH

3.3.1 Power-Off

When the core supply voltage is at or below the V

(low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation.

3.3.2 Low Power Hardware Data Protection

When V

is less than V

(cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

Single Latency (Dummy) Cycle ≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X Z X

Single Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X MV X

Dual Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X HV HV

Dual Latency (Dummy) Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X X X

Dual Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X MV MV

QPP Address Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X HV

Quad Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HV HV HV HV

Quad Latency (Dummy) Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X X

Quad Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV MV MV MV

DDR Single Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X HV

DDR Dual Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X HV HV

DDR Quad Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HV HV HV HV

DDR Latency (Dummy) Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV or Z MV or Z MV or Z MV or Z

DDR Single Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL Z Z MV X

DDR Dual Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL Z Z MV MV

DDR Quad Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV MV MV MV

Table 3. Interface States Summary (Continued)

Interface State V

RESET# SCK CS#

HOLD# /

I/O3

WP# / z

I/O2

SO /

I/O1

SI /

I/O0

Document Number: 001-98284 Rev. *M Page 20 of 134

S25FL512S

3.3.3 Power-On (Cold) Reset

When the core voltage supply remains at or below the V

(low) voltage for  t

time, then rises to  V

CC (Minimum)

the device will

begin its Power-On Reset (POR) process. POR continues until the end of t

. During t

the device does not react to external input

signals nor drive any outputs. Following the end of t

the device transitions to the Interface Standby state and can accept

commands. For additional information on POR see Power-On (Cold) Reset on page 29.

3.3.4 Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven low for t

time the device starts the

hardware reset process. The process continues for t

RPH

time. Following the end of both t

RPH

and the reset hold time following the

rise of RESET# (t

) the device transitions to the Interface Standby state and can accept commands. For additional information on

hardware reset see POR followed by Hardware Reset on page 29.

3.3.5 Interface Standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning

of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command.

While in interface standby state the memory device draws standby current (I

) if no embedded algorithm is in progress. If an

embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to

standby current draw.

3.3.6 Instruction Cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of

the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance

bit of the 8 bit instruction. The host keeps RESET# high, CS# low, HOLD# high, and drives Write Protect (WP#) signal as needed for

the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.

The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.

The expected next interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the

rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.7 Hold

When Quad mode is not enabled (CR[1]=0) the HOLD# / I/O3 signal is used as the HOLD# input. The host keeps RESET# high,

HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a command is paused, as though

SCK were held low. SI / I/O0 and SO / I/O1 ignore the input level when acting as inputs and are high impedance when acting as

outputs during hold state. Whether these signals are input or output depends on the command and the point in the command

sequence when HOLD# is asserted low.

When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.

When Quad mode is enabled the HOLD# / I/O3 signal is used as I/O3.

During DDR commands the HOLD# and WP# inputs are ignored.

3.3.8 Single Input Cycle - Host to Memory Transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The

dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The

host keeps RESET# high, CS# low, HOLD# high, and drives SI as needed for the command. The memory does not drive the Serial

Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory

using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.

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