Cypress S25FL512S 3.0V SPI Flash Memory详细规格

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"S25FL512S是一款由Cypress Semiconductor Corporation生产的串行SPI闪存芯片，具有512Mbit（等同于64Mbyte）的存储容量。这款芯片设计为3.0V CMOS核心，支持多种I/O功能。其特点包括SPI接口与Multi-I/O功能，提供不同的SPI时钟极性和相位模式，以及双数据率（DDR）选项。此外，它还具备扩展地址空间，能够处理32位地址。" S25FL512S的命令集和引脚布局兼容S25FL-A、S25FL-K和S25FL-PSPI系列，同时其Multi-I/O命令集与S25FL-PSPI家族产品兼容，这意味着它可以无缝集成到这些系列的系统中。该芯片在读取操作方面非常灵活，支持正常、快速、双线、四线、快速DDR、双线DDR和四线DDR等多种读取模式。其中，自动启动功能允许在电源开启或复位后自动执行预设地址的正常或四线读取命令。为了配置信息，S25FL512S还包含了通用闪存接口（CFI）数据。在编程方面，它的速度可达1.5MBps，配备512字节的页编程缓冲区，适合慢速时钟系统。它还支持四输入页编程（QPP）。为了提高数据的可靠性，S25FL512S内置了自动ECC（错误校验码），能够实现单比特错误修正，确保数据的完整性。在擦除功能上，该芯片提供了均匀的256-kByte块擦除，且速度在0.5到0.65MBps之间。此外，它还支持更小的4-kByte扇区擦除，这使得局部数据更新更加灵活。这种高密度、高性能的SPI闪存适用于各种嵌入式系统，如嵌入式控制器、物联网设备、工业控制系统等，这些系统需要大容量、高速度的非易失性存储解决方案。 S25FL512S是一款高性能的串行闪存芯片，具备丰富的功能和高可靠性，适用于对存储有严格要求的现代电子系统。其特性涵盖了广泛的读取模式、高效编程和擦除功能，以及内置的错误校正机制，确保了数据的快速访问和安全存储。

Document Number: 001-98284 Rev. *Q Page 16 of 145

S25FL512S

Figure 11. Single Bit Wide I/O Command with Latency

Figure 12. Dual Output Command

Figure 13. Quad Output Command without Latency

Figure 14. Dual I/O Command

Figure 15. Quad I/O Command

CS#

SCK

Phase

7 6 5 4 3 2 1 0 31 1 0

7 6 5 4 3 2 1 0

Instruction Dummy Cycles Data 1Address

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0

30 28 26

0 6 4 2 0 6 4 2 0

31 29 27

1 7 5 3 1 7 5 3 1

Instruction 6 Dummy Data 1 Data 2Address

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 4 0 4 0 4 0 4

5 1 5 1 5 1 5 1 5 1 5

6 2 6 2 6 2 6 2 6 2 6

7 3 7 3 7 3 7 3 7 3 7

Instruction Address

Data 1 Data 2 Data 3 Data 4 Data 5

...

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0

31 3 1 7 5 3 1 7 5 3 1

Instruction Address Dummy Data 1 Data 2

CS#

SCK

IO0

IO1

IO2

IO3

Phase

7 6 5 4 3 2 1 0 28 4 0 4 4 0 4 0 4 0 4 0

29 5 1 5 5 1 5 1 5 1 5 1

30 6 2 6 6 2 6 2 6 2 6 2

31 7 3 7 7 3 7 3 7 3 7 3

Instruction Address Mode Dummy D1 D2 D3 D4

Document Number: 001-98284 Rev. *Q Page 18 of 145

S25FL512S

Legend:

Z = no driver - floating signal

HL = Host driving V

HH = Host driving V

HV = either HL or HH

X = HL or HH or Z

HT = Toggling between HL and HH

ML = Memory driving V

MH = Memory driving V

MV = either ML or MH

Hold Cycle ≥ V

(min)

≥ V

(min)

≤ V

HH HV or HT HL HL X X X

Single Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X Z HV

Single Latency (Dummy)

Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X Z X

Single Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X MV X

Dual Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X HV HV

Dual Latency (Dummy)

Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X X X

Dual Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HH X MV MV

QPP Address Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X HV

Quad Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HV HV HV HV

Quad Latency (Dummy)

Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X X

Quad Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV MV MV MV

DDR Single Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X X HV

DDR Dual Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL X X HV HV

DDR Quad Input Cycle

Host to Memory Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL HV HV HV HV

DDR Latency (Dummy)

Cycle

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV or Z

MV or

DDR Single Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL Z Z MV X

DDR Dual Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL Z Z MV MV

DDR Quad Output Cycle

Memory to Host Transfer

≥ V

(min)

≥ V

(min)

≤ V

HH HT HL MV MV MV MV

Table 3. Interface States Summary (Continued)

Interface State V

RESET# SCK CS#

HOLD# /

I/O3

WP# /

I/O2

SO /

I/O1

SI /

I/O0

Document Number: 001-98284 Rev. *Q Page 19 of 145

S25FL512S

3.3.1 Power-Off

When the core supply voltage is at or below the V

(low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation.

3.3.2 Low Power Hardware Data Protection

When V

is less than V

(cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.3.3 Power-On (Cold) Reset

When the core voltage supply remains at or below the V

(low) voltage for  t

time, then rises to  V

CC (Minimum)

the device will

begin its Power-On Reset (POR) process. POR continues until the end of t

. During t

the device does not react to external input

signals nor drive any outputs. Following the end of t

the device transitions to the Interface Standby state and can accept

commands. For additional information on POR see Power-On (Cold) Reset on page 29.

3.3.4 Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven low for t

time the device starts the

hardware reset process. The process continues for t

RPH

time. Following the end of both t

RPH

and the reset hold time following the

rise of RESET# (t

) the device transitions to the Interface Standby state and can accept commands. For additional information on

hardware reset see POR followed by Hardware Reset on page 29.

3.3.5 Interface Standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning

of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command.

While in interface standby state the memory device draws standby current (I

) if no embedded algorithm is in progress. If an

embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to

standby current draw.

3.3.6 Instruction Cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of

the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance

bit of the 8 bit instruction. The host keeps RESET# high, CS# low, HOLD# high, and drives Write Protect (WP#) signal as needed for

the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.

Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.

The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.

The expected next interface state depends on the instruction received.

Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the

rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.7 Hold

When Quad mode is not enabled (CR[1]=0) the HOLD# / I/O3 signal is used as the HOLD# input. The host keeps RESET# high,

HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a command is paused, as though

SCK were held low. SI / I/O0 and SO / I/O1 ignore the input level when acting as inputs and are high impedance when acting as

outputs during hold state. Whether these signals are input or output depends on the command and the point in the command

sequence when HOLD# is asserted low.

When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.

When Quad mode is enabled the HOLD# / I/O3 signal is used as I/O3.

During DDR commands the HOLD# and WP# inputs are ignored.

Document Number: 001-98284 Rev. *Q Page 20 of 145

S25FL512S

3.3.8 Single Input Cycle - Host to Memory Transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The

dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The

host keeps RESET# high, CS# low, HOLD# high, and drives SI as needed for the command. The memory does not drive the Serial

Output (SO) signal.

The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory

using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.

3.3.9 Single Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During

the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host

may drive the SI signal during these cycles or the host may leave SI floating. The memory does not use any data driven on SI / I/O0

or other I/O signals during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the

falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that

there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents

driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (SO) or I/

O signals during the latency cycles.

The next interface state depends on the command structure, that is the number of latency cycles, and whether the read is single,

dual, or quad width.

3.3.10 Single Output Cycle - Memory to Host Transfer

Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps RESET# high, CS#

low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal. The memory

drives SO with data.

The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the command.

3.3.11 Dual Input Cycle - Host to Memory Transfer

The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps RESET# high, CS#

low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives address on SI / I/O0 and SO / I/O1.

The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency cycles needed or

Dual Output Cycle if no latency is required.

3.3.12 Dual Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before

transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During

the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host

may drive the SI / I/O0 and SO / I/O1 signals during these cycles or the host may leave SI / I/O0 and SO / I/O1 floating. The memory

does not use any data driven on SI / I/O0 and SO / I/O1 during the latency cycles. The host must stop driving SI / I/O0 and SO / I/O1

on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so

that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This

prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the SI / I/O0 and

SO / I/O1 signals during the latency cycles.

The next interface state following the last latency cycle is a Dual Output Cycle.

3.3.13 Dual Output Cycle - Memory to Host Transfer

The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET# high, CS# low, and

HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / I/O0 and SO / I/O1 signals during the

dual output cycles.

The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the command.

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