I2C总线协议V2.1详解：设计与制造商的福音

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I2C总线协议规范V2.1是Philips Semiconductors在1999年发布的标准，该版本是对1992年和1983年版本的更新。它是一种串行通信接口，旨在简化设计者和制造商之间的硬件连接，并提高设备间的通信效率。这份规范详细阐述了I2C（Inter-Integrated Circuit）系统的基本原理、数据传输机制、地址识别、仲裁和同步、以及扩展模式，如高速模式（Fast Mode）和高频率模式（Hs-Mode）。 1. **版本更新**： - V1.0于1992年发布，V2.0在1983年确立，V2.1在1999年带来了重要改进和扩展，体现了对技术演进的响应。 2. **设计者和制造商的益处**： - 设计者可以从I2C简单易用的接口中受益，它减少了接口复杂性，便于集成多种设备。 - 制造商则可以利用I2C的标准化设计，降低成本，提高互操作性，支持广泛的设备兼容性。 3. **I2C-bus概念与特性**： - I2C通过两条信号线（SDA和SCL）进行通信，数据线SDA用于传输数据，时钟线SCL控制数据传输的节奏。 - 数据传输包括起始（START）、停止（STOP）、地址识别、数据传输及确认（ACK）等步骤。 4. **数据传输**： - 数据以字节为单位传输，每个字节包含7位地址和1位读写指示。 - 接收端根据发送端的ACK信号确认数据接收正确。 5. **仲裁和时钟管理**： - I2C采用仲裁机制来解决多设备同时发送数据的问题，通过比较各自信号的优先级决定数据传输。 - 同步机制确保所有设备在正确的时机进行数据交换。 6. **7位地址编码**： - 7位地址区分不同的I2C设备，包括通用呼叫地址、START字节和CBUS兼容性考虑。 7. **扩展模式**： - 快速模式（Fast Mode）提供更快的数据传输速率，适用于对延迟敏感的应用。 - 高速模式（Hs-Mode）进一步提升速度，并引入了新的数据传输格式，允许连续的数据流。 I2C总线协议V2.1的规范提供了丰富的细节，使得设计者能够充分利用其高效、灵活的特性来构建低功耗、低成本的嵌入式系统，同时也方便了不同设备间的通信整合。无论是初学者还是高级工程师，这份规范都是深入理解和实现I2C通信的基础文档。

Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

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